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| 1. description the m37281mah?xxsp, m37281mfh?xxsp and m37281mkh- xxxsp are single-chip microcomputers designed with cmos silicon gate technology. they have a osd function and a data slicer func- tion, so it is useful for a channel selection system for tv with a closed caption decoder. the feautures of the m37281eksp is similar to those of the m37281mkh-xxxsp except that the chip has a built-in prom which can be written electrically. the difference between m37281mah xxxsp, m37281mkh-xxxsp and M37281MFH-XXXSP are the rom size and ram size. accordingly, the following descriptions will be for the m37281mkh-xxxsp. 2. features number of basic instructions .................................................... 71 memory size rom .................. 40k bytes (m37281mah-xxxsp) 60k bytes (M37281MFH-XXXSP) 80k bytes (m37281mkh-xxxsp, m37281eksp) ram ................... 1088 bytes (m37281mah-xxxsp, M37281MFH-XXXSP) 1536 bytes (m37281mkh-xxxsp, m37281eksp) (*rom correction memory included) minimum instruction execution time ......................................... 0.5 s (at 8 mhz oscillation frequency) power source voltage ................................................. 5 v ?10 % subroutine nesting ............................................. 128 levels (max.) interrupts ....................................................... 19 types, 16 vectors 8-bit timers .................................................................................. 6 programmable i/o ports (ports p0, p1, p2, p3 0 , p3 1 ) ............. 26 input ports (ports p4 0 ?4 6 , p6 3 , p6 4 , p7 0 ?7 2 ) ...................... 12 output ports (ports p5 2 ?5 5 ) ..................................................... 4 led drive ports ........................................................................... 2 serial i/o ............................................................ 8-bit ? 1 channel multi-master i 2 c-bus interface .............................. 1 (2 systems) a-d converter (8-bit resolution) .................................... 8 channels pwm output circuit ......................................................... 8-bit ? 8 power dissipation in high-speed mode ......................................................... 165 mw (at v cc = 5.5v, 8 mhz oscillation frequency, osd on, and data slicer on) in low-speed mode ......................................................... 0.33 mw (at v cc = 5.5v, 32 khz oscillation frequency) rom correction function ................................................ 2 vectors closed caption data slicer osd function display characters .... 32 characters ? 16 lines + ram font (1 character) (cc/osd mode)(cdosd mode)(ram font) kinds of characters ......... 510 kinds + 62 kinds + 1 kind (coloring unit) (a character) (a dot) (a dot) triple layer function ....................................................................... 2 layers selected from cc/cdosd/osd mode + ram font layer character display area .............. cc/cdosd mode: 16 ? 26 dots osd mode/ram font: 16 ? 20 dots kinds of character sizes .................... cc mode/ram font: 4 kinds osd/cdosd mode: 14 kinds kinds of character colors .............................................................. 64 colors (4 adjustment levels for each r, g, b) coloring unit ............ dot, character, character background, raster blanking output out1, out2 display position horizontal: 256 levels vertical :1024 levels (ram font can be set independently) attribute ........................................................................................ cc mode: smooth italic, underline, flash, automatic solid space osd mode: border, shadow window/blank function 3. application tv with a closed caption decoder single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rej03b0049-0101z rev.1.01 2003.07.16 rev.1.01 2003.07.16 page 1 of 171
m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 2 of 170 table of contents 1. description .......................................................................... 1 2. features ................................................................................ 1 3. application ........................................................................... 1 4. pin configuration .............................................................. 3 5. functional block diagram ............................................. 4 6. performance overview .................................................. 5 7. pin description ................................................................... 7 8. functional description ................................................ 11 8.1 central processing unit (cpu) ............................. 11 8.2 memory .......................................................................... 12 8.3 interrupts .................................................................... 21 8.4 timers ............................................................................. 26 8.5 serial i/o ........................................................................ 30 8.6 multi-master i2c-bus interface ........................... 33 8.7 pwm output circuit .................................................. 46 8.8 a-d converter ............................................................. 50 8.9 rom correction function ..................................... 54 8.10 data slicer .................................................................. 55 8.11 osd functions ........................................................... 66 8.11.1 triple layer osd ................................................... 71 8.11.2 display position ..................................................... 74 8.11.3 dot size ................................................................. 78 8.11.4 clock for osd ....................................................... 79 8.11.5 field determination display .................................. 81 8.11.6 memory for osd ................................................... 83 8.11.7 character color ..................................................... 91 8.11.8 character background color ................................. 91 8.11.9 out1, out2 signals ............................................ 95 8.11.10 attribute ............................................................... 96 8.11.11 automatic solid space function ........................ 101 8.11.12 multiline display ................................................ 102 8.11.13 sprite osd function ...................................... 103 8.11.14 window function ............................................... 107 8.11.15 blank function ................................................. 108 8.11.16 raster coloring function .................................. 113 8.11.17 scan mode ........................................................ 115 8.11.18 osd output pin control .................................... 116 8.12. software runaway detect func-tion .......... 117 8.13. reset circuit .......................................................... 118 8.14 clock generating circuit .................................. 119 8.15. display oscillation circuit ............................... 122 8.16. auto-clear circuit ............................................... 122 8.17. addressing mode .................................................. 122 8.18. machine instructions ......................................... 122 9. programming notes ...................................................... 122 10. absolute maximum ratings ....................................... 123 11. recommended operating conditions ................... 123 12. electric characteristics ........................................ 124 13. analog r, g, b output characteristics ............... 126 14. a-d converter characteristics ............................. 126 15. multi-master i2c-bus bus line characteristics ......... 127 16. prom programming method ..................................... 128 17. data required for mask orders ............................ 129 18. appendix ........................................................................... 130 19. package outline ........................................................... 170 rev.1.01 2003.07.16 page 3 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp 4. pin configuration outline 52p4b fig. 4.1 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 hlf/ad6 h sync v sync p4 0 /ad4 p4 1 /int2 p4 2 /tim2 p4 3 /tim3 p2 4 /ad3 p2 5 /ad2 p0 1 /pwm5 p0 2 /pwm6 p1 7 /s in /r0 p4 4 /int1 p4 6 /s clk p7 2 /(s in ) p5 2 /r/r1 p5 3 /g/g1 p5 4 /b/b1 p5 5 /out1 p0 4 /pwm0 p0 5 /pwm1 p1 0 /out2 p1 1 /scl1 p1 2 /scl2 p1 3 /sda1 p1 4 /sda2 p1 5 /g0 p1 6 /int3/b0 p3 0 /ad7 p3 1 /ad8 reset p6 4 /osc2/x cout p6 3 /osc1/x cin v cc p0 3 /pwm7 p2 6 /ad1 p2 7 /ad5 p0 0 /pwm4 p4 5 /s out p0 6 /pwm2 p2 1 p2 2 p2 3 17 18 19 20 37 36 35 34 33 m37281mah-xxxsp, M37281MFH-XXXSP, m37281mkh-xxxsp, m37281eksp p7 0 /cv in p7 1 /v hold cnv ss x out x in v ss 21 22 23 24 25 26 32 31 30 29 28 27 p0 7 /pwm3 p2 0 ( )...m37281eksp (av cc ) nc note : only 18th pin is nc pin of m37281mah/ mfh/mkh-xxxsp. this pin is avcc pin of m37281eksp. but nc pin of m37281mah/mfh/mkh-xxxsp is not connect in the ic. you can apply to vcc. m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 4 of 170 5. functional block diagram fig. 5.1 functional block diagram of m37281 ( )... m37281eksp (av cc ) nc clock input clock output x in x out reset input v cc v ss cnv ss pins for data slicer clock output for osd/ sub-clock output input ports p6 3 , p6 4 osc1/x cin osc2/x out clock input for osd/ sub-clock input p1 (8) multi-master i 2 c-bus interface p3 (2) sda1 scl2 scl1 sda2 p2 (8) p0 (8) p4 (7) s in s clk s out si/o (8) int1 int2 h sync v sync a-d converter 8-bit arithmetic and logical unit accumulator a (8) timer 6 t6 (8) timer 5 t5 (8) timer 4 t4 (8) timer 3 t3 (8) timer 2 t2 (8) timer 1 t1 (8) timer count source selection circuit tim2 tim3 data slicer instruction register (8) instruction decoder control signal processor status register ps (8) stack pointer s (8) index register y (8) index register x (8) rom program counter pc l (8) progam counter pc h (8) ram data bus clock generating circuit 24 35 30 reset 18 27 26 23 cv in 22 21 19 20 v hold hlf 28 29 address bus 32 14 34 35 36 37 38 39 40 10 9 8 7 41 42 43 44 45 46 47 48 33 13 12 11 17 16 15 6 5 4 3 2 1 i/o ports p3 0 , p3 1 i/o port p1 i/o port p2 i/o port p0 input ports p4 0 ?4 6 p5 (4) out1 b g r 49 50 51 52 output port p5 2 ?5 5 sync signal input int3 pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 8-bit pwm circuit pwm7 31 input ports p7 0 p7 2 a-d converter si/o p7 (3) osd circuit osd circuit p6(2) osd circuit rev.1.01 2003.07.16 page 5 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp number of basic instructions instruction execution time clock frequency memory size input/output ports serial i/o multi-master i 2 c-bus interface a-d converter pwm output circuit timers rom correction function subroutine nesting interrupt clock generating circuit data slicer rom ram osd rom (character font) osd rom (color dot font) osd ram (sprite) osd ram (character) p0 0 ?0 2 , p0 4 ?0 7 p0 3 p1 0 , p1 5 ?1 7 p1 1 ?1 4 p2 p3 0 , p3 1 p4 0 ?4 4 p4 5 , p4 6 p5 2 ?5 5 p6 3 p6 4 p7 0 ?7 2 i/o i/o i/o i/o i/o i/o input input output input input input 71 0.5 s (the minimum instruction execution time, at 8 mhz oscillation fre- quency) 8 mhz (maximum) 40k bytes 60k bytes 80k bytes 1088 bytes (rom correction memory included) 1536 bytes (rom correction memory included) 20400 bytes 9672 bytes 120 bytes 1536 bytes 7-bit ? 1 (n-channel open-drain output structure, can be used as pwm output pins) 1-bit ? 1 (cmos input/output structure, can be used as pwm output pin) 4-bit ? 1 (cmos input/output structure, can be used as osd output pin, int input pin, serial input pin) 4-bit ? 1 (n-channel open-drain output structure, can be used as multi- master i 2 c-bus interface) 8-bit ? 1 (cmos input/output structure, can be used as a-d input pins) 2-bit ? 1 (cmos input/output structure, can be used as a-d input pins) 5-bit ? 1 (can be used as a-d input pins, int input pins, external clock input pins for timer) 2-bit ? 1 (n-channel open-drain output structure when serial i/o is used, can be used as serial i/o pins) 4-bit ? 1 (cmos output structure, can be used as osd output pins) 1-bit ? 1 (can be used as sub-clock input pin, osd clock input pin) 1-bit ? 1 (cmos output structure when lc is oscillating, can be used as sub-clock output pin, osd clock output pin) 3-bit ? 1 (can be used as data slicer input/output, serial input pin) 8-bit ? 1 1 (2 systems) 8 channels (8-bit resolution) 8-bit ? 8 8-bit timer ? 6 2 vectors 128 levels (maximum) <19 types> int external interrupt ? 3, internal timer interrupt ? 6, serial i/o interrupt ? 1, osd interrupt ? 1, multi-master i 2 c-bus interface interrupt ? 1, data slicer interrupt ? 1, f(x in )/4096 interrupt ? 1, sprite osd interrupt ? 1, v sync interrupt ? 1, a-d conversion interrupt ? 1, brk instruction inter- rupt ? 1, reset ? 1 2 built-in circuits (externally connected to a ceramic resonator or a quartz- crystal oscillator) built in parameter 6. performance overview m37281mah-xxxsp M37281MFH-XXXSP m37281mkh-xxxsp, m37281eksp m37281mah-xxxsp,M37281MFH-XXXSP m37281mkh-xxxsp, m37281eksp table 6.1 performance overview functions m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 6 of 170 power source voltage power dissipation number of display characters dot structure kinds of characters kinds of character sizes character font coloring display position functions table 6.2 performance overview osd function 32 characters ? 16 lines cc mode: 16 ? 26 dots (character display area: 16 ? 20 dots) osd mode: 16 ? 20 dots exosd mode: 16 ? 26 dots sprite display: 16 ? 20 dots cc/osd mode: 510 kinds cdosd mode: 62 kinds sprite display: 1 kind cc mode: 4 kinds osd/cdosd mode: 14 kinds sprite display: 8 kinds rev.1.01 2003.07.16 page 7 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp v cc , (av cc ,) v ss cnv ss reset x in x out p0 0 / pwm4 p0 2 /pwm6, p0 3 /pwm7, p0 4 / pwm0 p0 7 /pwm3 p1 0 /out2, p1 1 /scl1, p1 2 /scl2, p1 3 /sda1, p1 4 /sda2, p1 5 /g0, p1 6 /int3/ b0, p1 7 /s in /r0 p2 0 ?2 3 p2 4 /ad3 p2 6 /ad1 , p2 7 /ad5 p3 0 /ad7, p3 1 /ad8 p4 0 /ad4, p4 1 /int2, p4 2 /tim2, p4 3 /tim3, p4 4 /int1, p4 5 /s out , p4 6 /s clk input input output i/o output i/o output i/o input input i/o input i/o input input input input input output i/o apply voltage of 5 v ?10 % (typical) to v cc (av cc ) , and 0 v to v ss . ( ) ...m37281eksp connected to v ss . to enter the reset state, the reset input pin must be kept at a low for 2 s or more (under normal v cc conditions). if more time is needed for the quartz-crystal oscillator to stabilize, this low condition should be maintained for the required time. this chip has an internal clock generating circuit. to control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins x in and x out . if an external clock is used, the clock source should be connected to the x in pin and the x out pin should be left open. port p0 is an 8-bit i/o port with direction register allowing each i/o bit to be individually programmed as input or output. at reset, this port is set to input mode. the output structure of p0 3 is cmos output, that of p0 0 ?0 2 and p0 4 ?0 7 are n-channel open-drain output (see note.) pins p0 0 ?0 3 and p0 4 ?0 7 are also used as 8-bit pwm output pins pwm4?wm7 and pwm0?wm3 respectively. the output structure of pwm0?wm6 is n-channel open-drain output. and the output structure of pwm7 is cmos output. port p1 is an 8-bit i/o port and has basically the same functions as port p0. the output structure of p1 0 and p1 5 ?1 7 is cmos output, that of p1 1 ?1 4 is n-channel open-drain output (see note.) pin p1 0 , p1 5 ?1 7 are also used as osd output pins out2, g0, b0, r0, respectively. the output structure is cmos output. pin p1 1 ?1 4 are used as scl1, scl2, sda1 and sda2 respectively, when multi-master i 2 c-bus interface is used. the output structure is n-channel open-drain output. pin p1 6 is also used as int extemal interrupt input pin int3. pin p1 7 is also used as serial i/o data input pin s in . port p2 is an 8-bit i/o port and has basically the same functions as port p0. the output structure is cmos output (see note.) pins p2 4 ?2 6 , p2 7 are also used as analog input pins ad3?d1, ad5 respectively. ports p3 0 and p3 1 are 2-bit i/o ports and have basically the same functions as port p0. the output structure is cmos output (see note.) pins p3 0 , p3 1 are also used as analog input pins ad7, ad8 respectively. ports p4 0 ?4 6 are a 7-bit input port. pin p4 0 is also used as analog input pin ad4. pins p4 1 , p4 4 are also used as int external interrupt input pins int2, int1. pins p4 2 and p4 3 are also used as int external clock input pins tim2, tim3 for timer respectively. pin p4 5 is used as serial i/o data output pin s out . the output structure is n-channel open- drain output. pin p4 6 is used as serial i/o synchronous clock input/output pin s clk . the output structure is n-channel open-drain output. pin name functions input/ output power source cnv ss reset input clock input clock output i/o port p0 8-bit pwm output i/o port p1 osd output multi-master i 2 c-bus interface external interrupt input serial i/o data input i/o port p2 analog input i/o port p3 analog input input port p4 analog input external interrupt input external clock input for timer serial i/o data output serial i/o synchronous clock input/output 7. pin description table 7.1 pin description m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 8 of 170 table 7.2 pin description (continued) note : port pi (i = 0 to 3) has the port pi direction register (address 00c1 16 of zero page) which can be used to program each bit as an input (?? or an output (??. the pins programmed as ??in the direction register are output pins. when pins are programmed as ?,?they are input pins. whe n pins are programmed as output pins, the output data are written into the port latch and then output. when data is read from the output pins, the outpu t pin level is not read but the data of the port latch is read. this allows a previously-output value to be read correctly even if the output ??voltage has risen, for example, because a light emitting diode was directly driven. the input pins float, so the values of the pins can be read. when data is written into the input pin , it is written only into the port latch, while the pin remains in the floating state. input/ output output port p5 osd output input port p6 clock input for osd clock output for osd sub-clock input sub-clock output input port p7 input for data slicer serial i/o data input i/o for data slicer analog input h sync input v sync input port p5 is a 4-bit output port. the output structure is cmos output. pins p5 2 ?5 5 are also used as osd output pins r/r1, g/g1, b/b1, out1 respectively. at r, g, b output, the output structure is analog output. at r1, g1, b1 and out1 output, the output structure is cmos output. ports p6 3 and p6 4 are 2-bit input port. pin p6 3 is also used as osd clock input pin osc1. pin p6 4 is also used as osd clock output pin osc2. the output structure is cmos output. pin p6 3 is also used as sub-clock input pin x cin . pin p6 4 is also used as sub-clock output pin x cout . the output structure is cmos output. ports p7 0 ?7 2 are 3-bit input port. pins p7 0 , p7 1 are also used as data slicer input pins cv in , v hold respectively. when using data slicer, input composite video signal through a capacitor. connect a capacitor between v hold and v ss . pins p7 2 is also used as serial i/o data input pin s in . when using data slicer, connect a filter using of a capacitor and a resistor between hlf and v ss . this is an analog input pin ad6 . this is a horizontal synchronous signal input for osd. this is a vertical synchronous signal input for osd. pin name functions output output input input output input output input input input i/o input input input p7 0 /cv in, p7 1 /v hold , p7 2 /(s in ) hlf/ad6 h sync v sync p6 3 /osc1/ x cin , p6 4 /osc2/ x cout p5 2 /r/r1, p5 3 /g/g1, p5 4 /b/b1, p5 5 /out1 rev.1.01 2003.07.16 page 9 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp fig. 7.1 i/o pin block diagram (1) n-channel open-drain output ports p0 0 ?0 2 , p0 4 ?0 7 note1 : each port is also used as follows : p0 0 ?0 2 : pwm4?wm6 p0 4 ?0 7 : pwm0?wm3 2 : m37281eksp, does not have the diode side with v cc . n-channel open-drain output port p1 1 -p1 4 note : each port is also used as follows : p1 1 : scl1 p1 2 : scl2 p1 3 : sda1 p1 4 : sda2 cmos output ports p0 3 , p1 0 , p1 5 ?1 7 , p2, p3 0 , p3 1 note : each port is also used as follows : p0 0 : pwm7 p1 0 : out2 p1 5 : g0 p1 6 : int3/b0 p1 7 : s in /r0 p2 4 ?2 6 : ad3?d1 p2 7 : ad5 p3 0 : ad7 p3 1 : ad8 p0 3 , p1 0 , p1 5 p1 7 , p2, p3 0 , p3 1 data bus direction register port latch data bus direction register port latch data bus direction register port latch p0 0 p0 2 , p0 4 p0 7 p1 1 p1 4 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 10 of 170 n-channel open-drain output ports p4 5 , p4 6 note : each pin is also used as follows : p4 5 : s out p4 6 : s clk cmos output port p5 5 note : port p5 5 is also used as pin out1. schmidt input h sync , v sync fig. 7.2 i/o pin block diagram (2) h sync , v sync s out , s clk port p5 5 data bus direction register internal circui t data bus ports p4 0 p4 4 internal circui t internal circuit ports p5 2 p5 4 output ports p5 2 ?5 4 note : each port is also used as follows : p5 2 : r/r1 p5 3 : g/g1 p5 4 : b/b1 input ports p4 0 ?4 4 note : each port is also used as follows : p4 0 : ad4 p4 1 : int2 p4 2 : tim2 p4 3 : tim3 p4 4 : int1 rev.1.01 2003.07.16 page 11 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp 8. functional description 8.1. central processing unit (cpu) this microcomputer uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine instructions or the series 740 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 12 of 170 8.2 memory 8.2.1 special function register (sfr) area the special function register (sfr) area in the zero page contains control registers such as i/o ports and timers. 8.2.2 ram ram is used for data storage and for stack area of subroutine calls and interrupts. 8.2.3 rom the m37281mah-xxxsp has 40k-byte program area and M37281MFH-XXXSP has 60k-byte program area. the m37281mkh -xxxsp has 56k-byte program area and 24k-byte data-dedicated area. for the m37281eksp, the two area (60k, 24k + 56k) can be swithed each other by setting the bank control register. 8.2.4 osd ram ram for display is used for specifying the character codes and col- ors to display. 8.2.5 osd rom rom for display is used for storing character data. 8.2.6 interrupt vector area the interrupt vector area contains reset and interrupt vectors. 8.2.7 zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function registers (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. 8.2.8 special page the 256 bytes from addresses ff00 16 to ffff 16 are called the spe- cial page area. the special page addressing mode can be used to specify memory addresses in the special page area. access to this area with only 2 bytes is possible in the special page addressing mode. 8.2.9 rom correction vector this is used as the program jump destination addresses for rom correction. fig. 8.2.1 memory map (m37281mkh-xxxsp, m37281eksp) 0 0 0 0 1 6 0 0 c 0 1 6 0 0 f f 1 6 0 f f f 1 6 f f f f 1 6 f f d e 1 6 f f 0 0 1 6 0 8 0 0 1 6 1 0 8 0 0 1 6 1 f f f f 1 6 rom (60k bytes) o s d r a m ( c h a r a c t e r ) ( 1 5 3 6 b y t e s ) ( n o t e 2 ) 0 2 0 0 1 6 0 2 5 8 1 6 1 0 0 0 1 6 1 5 7 f f 1 6 1 8 0 0 0 1 6 1 0 0 0 0 1 6 s f r 1 a r e a s f r 2 a r e a n o t e s 1 : r e f e r t o t a b l e 8 . 1 1 . 6 o s d r a m ( s p r i t e ) . 2 : t a b l e s 8 . 1 1 . 4 a n d 8 . 1 1 . 5 o s d r a m ( c h a r a c t e r ) . 0 2 c 0 1 6 0 2 e 0 1 6 0 1 0 0 1 6 0 0 b f 1 6 0 7 0 0 1 6 0 7 a 7 1 6 o s d r a m ( s p r i t e ) ( 1 2 0 b y t e s ) ( n o t e 1 ) 1 a c f f 1 6 0 6 f f 1 6 ram (1536 bytes) 1 b 0 0 0 1 6 1c000 16 1 d 0 0 0 1 6 1 e 0 0 0 1 6 1 f 0 0 0 1 6 2 0 0 0 1 6 m37281mkh-xxxsp, m37281 eksp n o t u s e d n o t u s e d zero page e x t r a a r e a i n t e r r u p t v e c t o r a r e a special page r o m c o r r e c t i o n f u n c t i o n v e c t o r 1 : a d d r e s s 0 2 c 0 1 6 v e c t o r 2 : a d d r e s s 0 2 e 0 1 6 osd rom (character font) (20400 bytes) not used not used osd rom (color dot font) (9672 bytes) not used expansion rom (20k bytes) bank 11 b a n k 1 2 b a n k 1 3 b a n k 1 4 b a n k 1 5 rev.1.01 2003.07.16 page 13 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.2.2 memory map (m37281mah-xxxsp,M37281MFH-XXXSP) 0 0 0 0 1 6 0 0 c 0 1 6 00ff 16 0 f f f 1 6 ffff 16 f f d e 1 6 ff00 16 0 8 0 0 1 6 1 0 8 0 0 1 6 0 2 0 0 1 6 0 2 5 8 1 6 1000 16 1 5 7 f f 1 6 1 8 0 0 0 1 6 1 0 0 0 0 1 6 0 2 c 0 1 6 0 2 e 0 1 6 0100 16 00bf 16 0 7 0 0 1 6 0 7 a 7 1 6 1acff 16 0 5 3 f 1 6 m 3 7 2 8 1 m ah- x x x s p, rom (60k bytes) osd ram (character) (1536 bytes) (note 2) s f r 1 a r e a s f r 2 a r e a n o t e s 1 : r e f e r t o t a b l e 8 . 1 1 . 6 o s d r a m ( s p r i t e ) . 2 : t a b l e s 8 . 1 1 . 4 a n d 8 . 1 1 . 5 o s d r a m ( c h a r a c t e r ) . o s d r a m ( s p r i t e ) ( 1 2 0 b y t e s ) ( n o t e 1 ) ram (1088 bytes) n o t u s e d n o t u s e d z e r o p a g e e x t r a a r e a interrupt vector area special page rom correction function vector 1: address 02c0 16 vector 2: address 02e0 16 o s d r o m ( c h a r a c t e r f o n t ) ( 2 0 4 0 0 b y t e s ) not used not used osd rom (color dot font) (9672 bytes) not used 6000 16 rom (40k bytes) M37281MFH-XXXSP m37281mah-xxxsp, M37281MFH-XXXSP M37281MFH-XXXSP m37281mah-xxxsp m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 14 of 170 fig. 8.2.3 bank control register 8.2.10 expansion rom (only m37281mkh- xxxsp/m37281eksp) the m37281mkh-xxxsp/m37281eksp can use 5-bank (total 20k bytes) expansion rom (4k bytes each bank) by setting the bank register. the expansion rom is assigned to address 1b000 16 to 1ffff 16 . the contents of each bank in the expansion rom are read by setting the bank register and accessing addresses 1000 16 to 1fff 16 . as the expansion rom is not programmable, use it as data-dedicated area. when using the expansion rom area, the internal rom at addresses 1000 16 to 1fff 16 (extra area) is not also programmable. notes 1: when using the expansion rom (bk7 = 1 ), the rom correction function do not operate for addresses 1000 16 to 1fff 16 . 2: when using the emulator mcu (m37281erss), as addresses 1000 16 to ffff 16 can be emulated by setting bit 7 of the bank control regis- ter to 0, the expansion rom cannot be used. addresses 2000 16 to ffff 16 can be emulated by setting it to 1. the data in specified area by the bank selection bits can be read by accessing addresses 1000 16 to 1fff 16 . 3: when using the emulator mcu, the expansion rom and the extra area cannot be emulated by setting bit 7 of the bank control register to 1. therefore, write the data to this area before using. 4: for the m37281mkh-xxxsp, fix bit 7 of the bank control register to 1. for m37281mah-xxxsp and M37281MFH-XXXSP, fix the ad- dress 00ed 16 to 00 16 . b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b a n k c o n t r o l r e g i s t e r ( b k ) [ a d d r e s s 0 0 e d 1 6 ] b n a m e f unct i ons b a n k c o n t r o l r e g i s t e r 0 t o 3 6, 7 b an k contro l bits (bk6, bk7) b an k num b er i s se l ecte d (b an k 11 to 15 ) b an k selection bits (bk0 to bk3) 4 , 5 fi x t h ese bi ts to 0. a f t e r r e s e t r w 0 r w 0 r w 0 r w 0 ? 10 11 n ot use d u se d u se d r e a d o u t f r o m e x t r a a r e a ( p r o g r a m m a b l e ) r e a d o u t t h e d a t a f r o m a r e a s p e c i f i e d b y t h e b a n k s e l e c t i o n b i t s r e a d o u t f r o m e x t r a a r e a ( d a t a - d e d i c a t e d ) b 6 b an k rom a d d r e s s 1 0 0 0 1 6 l e v e l a c c e s s b 7 0 0 rev.1.01 2003.07.16 page 15 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.2.4 memory map of special function register 1 (sfr1) (1) d 0 1 6 d 1 1 6 d2 16 d 3 1 6 d 4 1 6 d 5 1 6 d6 16 d 7 1 6 d 8 1 6 d9 16 d a 1 6 d b 1 6 dc 16 d d 1 6 d e 1 6 d f 1 6 c0 16 c 1 1 6 c2 16 c 3 1 6 c4 16 c5 16 c6 16 c 7 1 6 c 8 1 6 c9 16 c b 1 6 c c 1 6 c d 1 6 ce 16 c f 1 6 ca 16 a d d r e s s p o r t p 5 ( p 5 ) osd control register 1 (oc 1) h o r i z o n t a l p o s i t i o n r e g i s t e r ( h p ) b l o c k c o n t r o l r e g i s t e r 1 ( b c 1 ) port p1 (p1) port p1 direction register (d1) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( d 3 ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( d 2 ) registe r p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( d 0 ) block control register 2 (bc 2 ) b l o c k c o n t r o l r e g i s t e r 3 ( b c 3 ) b l o c k c o n t r o l r e g i s t e r 4 ( b c 4 ) b l o c k c o n t r o l r e g i s t e r 5 ( b c 5 ) b l o c k c o n t r o l r e g i s t e r 6 ( b c 6 ) b l o c k c o n t r o l r e g i s t e r 7 ( b c 7 ) bit allocation state immediately after rese t p o r t p 4 ( p 4 ) port p4 direction register (d4) o s d p o r t c o n t r o l r e g i s t e r ( p f ) port p6 (p6) b l o c k c o n t r o l r e g i s t e r 8 ( b c 8 ) b l o c k c o n t r o l r e g i s t e r 9 ( b c 9 ) b l o c k c o n t r o l r e g i s t e r 1 0 ( b c 1 0 ) block control register 11 (bc 11 ) b l o c k c o n t r o l r e g i s t e r 1 2 ( b c 1 2 ) port p7 (p7) s f r 1 a r e a ( a d d r e s s e s c 0 1 6 t o d f 1 6 ) : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : < b i t a l l o c a t i o n > < s t a t e i m m e d i a t e l y a f t e r r e s e t > f u n c t i o n b i t : no function bit : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 immediately after reset : indeterminate immediately after reset 0 1 ? : 1 immediately after reset 1 0 b l o c k c o n t r o l r e g i s t e r 1 3 ( b c 1 3 ) block control register 14 (bc 14 ) b l o c k c o n t r o l r e g i s t e r 1 5 ( b c 1 5 ) b l o c k c o n t r o l r e g i s t e r 1 6 ( b c 1 6 ) b 7b 0b7 b0 ? 0 0 1 6 ? 0 0 1 6 ? 00 16 ? ? ? ? ? ? ? ? ? ? r 0 g b out1 out2 0 0? 0 0? ? 0 ? ? ? ? ? ? ? oc16 oc17 oc14 oc15 oc12 oc13 oc10 oc11 0 0 1 6 bc 1 0 bc 1 1 bc 1 2 bc 1 3 bc 1 4 bc 1 5 bc 1 6 b c 2 0 b c 2 1 bc 2 2 b c 2 3 bc 2 4 b c 2 5 b c 2 6 b c 3 0 b c 3 1 bc 3 2 b c 3 3 bc 3 4 b c 3 5 b c 3 6 b c 4 0 b c 4 1 bc 4 2 b c 4 3 bc 4 4 b c 4 5 b c 4 6 b c 5 0 b c 5 1 bc 5 2 b c 5 3 bc 5 4 b c 5 5 b c 5 6 bc 6 0 bc 6 1 bc 6 2 bc 6 3 bc 6 4 bc 6 5 bc 6 6 bc 7 0 bc 7 1 bc 7 2 bc 7 3 bc 7 4 bc 7 5 bc 7 6 b c 8 0 b c 8 1 bc 8 2 b c 8 3 bc 8 4 b c 8 5 b c 8 6 b c 9 0 b c 9 1 bc 9 2 b c 9 3 bc 9 4 b c 9 5 b c 9 6 b c 1 0 0 b c 1 0 1 b c 1 0 2 b c 1 0 3 b c 1 0 4 b c 1 0 5 b c 1 0 6 b c 1 1 0 b c 1 1 1 b c 1 1 2 b c 1 1 3 b c 1 1 4 b c 1 1 5 b c 1 1 6 b c 1 2 0 b c 1 2 1 b c 1 2 2 b c 1 2 3 b c 1 2 4 b c 1 2 5 b c 1 2 6 hp6 hp7 hp4 hp5 hp2 hp3 hp0 hp1 00 16 0 0 00 16 ? 0 0 1 6 ? 00 16 ? t 3 c s b c 1 3 0 b c 1 3 1 b c 1 3 2 b c 1 3 3 b c 1 3 4 b c 1 3 5 b c 1 3 6 b c 1 4 0 b c 1 4 1 b c 1 4 2 b c 1 4 3 b c 1 4 4 b c 1 4 5 b c 1 4 6 b c 1 5 0 b c 1 5 1 b c 1 5 2 b c 1 5 3 b c 1 5 4 b c 1 5 5 b c 1 5 6 b c 1 6 0 b c 1 6 1 b c 1 6 2 b c 1 6 3 b c 1 6 4 b c 1 6 5 b c 1 6 6 p6im rgb 2bit m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 16 of 170 fig. 8.2.5 memory map of special function register 1 (sfr2) (2) f 0 1 6 f 1 1 6 f 2 1 6 f 3 1 6 f 4 1 6 f 5 1 6 f 6 1 6 f 7 1 6 f 8 1 6 f 9 1 6 f a 1 6 f b 1 6 f c 1 6 f d 1 6 f e 1 6 f f 1 6 e 0 1 6 e 1 1 6 e 2 1 6 e 3 1 6 e 4 1 6 e 5 1 6 e 6 1 6 e7 16 e 8 1 6 e 9 1 6 e b 1 6 e c 1 6 e d 1 6 e e 1 6 e f 1 6 e a 1 6 d a t a s l i c e r c o n t r o l r e g i s t e r 1 ( d s c 1 ) a - d c o n v e r s i o n r e g i s t e r ( a d ) a - d c o n t r o l r e g i s t e r ( a d c o n ) t i m e r 1 ( t 1 ) c a p t i o n d a t a r e g i s t e r 1 ( c d 1 ) t i m e r 2 ( t 2 ) t i m e r 3 ( t 3 ) t i m e r 4 ( t 4 ) t i m e r m o d e r e g i s t e r 1 ( t m 1 ) t i m e r m o d e r e g i s t e r 2 ( t m 2 ) i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) i 2 c c o n t r o l r e g i s t e r ( s 1 d ) i 2 c clock control register (s2) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) interrupt request register 2 (ireq2) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) c p u m o d e r e g i s t e r ( c m ) d a t a s l i c e r c o n t r o l r e g i s t e r 2 ( d s c 2 ) i 2 c status register (s1) i 2 c address register (s0d) s f r 1 a r e a ( a d d r e s s e s e 0 1 6 t o f f 1 6 ) a d d r e s sr e g i s t e r bit allocation state immediately after rese t : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : < b i t a l l o c a t i o n > < state immediately after reset > function bit : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 immediately after reset : indeterminate immediately after reset 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 caption data register 2 (cd2) c a p t i o n d a t a r e g i s t e r 3 ( c d 3 ) c a p t i o n d a t a r e g i s t e r 4 ( c d 4 ) caption position register (cps) data slicer test register 2 data slicer test register 1 s ync s i gna l counter reg i ster (hc) cl oc k run- i n d etect reg i ster (crd) d a t a c l o c k p o s i t i o n r e g i s t e r ( d p s ) b7 b 0 b 7 b 0 tm20 tm21 t m 2 2 t m 2 3 tm24 tm10 tm11 t m 1 2 t m 1 3 tm14 cm2 tm1r tm2r t m 3 r t m 4 r osdr v s c r adr ck0 in1r dsr sior tm1e tm2e t m 3 e tm4e o s d e v s c e i n 1 e d s e s i o e in2e t m 2 5 ff 16 0 7 1 6 ff 16 0 7 1 6 t m 1 5 t m 1 6 tm17 t m 2 6 t m 2 7 ? sad0 s a d 1 s a d 2 sad3 s a d 4 sad5 s a d 6 rb w l r b a d 0 aas al pin bb t r x mst bc0 bc1 bc2 eso als bsel 0 bsel 1 ccr0 ccr1 ccr2 ccr3 ccr4 ac k 0 0 1 6 00 16 0 0 1 6 ck r in2r iicr t m 5 6 r ade cke iice t m 5 6 e t m 5 6 s 0 0 c m 7cm5 c m 6 adin0 adin1 adin2 a d v r e f a d s t r 1 0 b i t s a d 00 16 0 0 1 6 00 16 d s c 1 0 d s c 1 1 d s c 1 2 d s c 2 0 d s c 2 3 d s c 2 4 d s c 2 5 crd3 crd4 crd5 c r d 6 crd7 dps3 dps4 d p s 5 d p s 6 d p s 7 cps0 cps3 cps4 cps5 cps1 cps2 cps6 cps7 hc0 hc3 hc4 hc5 hc1 hc2 0? 0? 0 ? ?? 0 00 00 0 0 0 1 0 1 0 1 0 0 1 6 c d h 1 0 c d h 1 3 cdh14 c d h 1 5 cdh11 c d h 1 2 c d h 1 6 c d h 1 7 c d l 1 0 c d l 1 3 cdl14 cdl15 cdl11 cdl12 c d l 1 6 cdl17 00 16 0 0 1 6 00 16 0 0 1 6 00 16 00 16 00 16 0 0 1 6 00 16 d1 d2 d3 d4 d5 d6 d7 d0 0 0 00?00 0 0 0 0 01 0 0? fast mode a c k b i t 0 c d h 2 0 c d h 2 3 cdh24 c d h 2 5 cdh21 c d h 2 2 c d h 2 6 c d h 2 7 cdl20 cdl23 cdl24 cdl25 cdl21 cdl22 cdl26 cdl27 00 16 00 16 00 16 0 0 1 6 ? ? 0 0 0? 001 0 0 9 1 6 3 c 1 6 0 b a n k c o n t r o l r e g i s t e r ( b k ) bk0 b k 3b k 1 b k 2 bk6 bk7 00 ? ? 00??? ? rev.1.01 2003.07.16 page 17 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.2.6 memory map of special function register 2 (sfr2) (1) : : < s t a t e i m m e d i a t e l y a f t e r r e s e t > : n a m e : : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 b 7b 0b 7b0 0 0 1 6 ? ? ? ? ? ? ? 0 0 1 6 0 0 1 6 0 0 1 6 p w 0 p w 1 p w 2 p w 3 p w 4 p w 5 p w 6 p n 3 r e 1 r e 2 r e 3 r e 5 i n t 3 p o l a d / i n t 3 s e l p o l 3 a d / i n t 3 s e l s m 0 r e 1 r e 2 r e 3 s m 4 r e 5 i n t 3 p o l a d / i n t 3 s e l s m 1 s m 2 s m 3 s m 5 p c 0 r e 1 r e 2 r e 3 p c 4 r e 5 i n t 3 p o l a d / i n t 3 s e l p c 1 p c 2 p c 5 p c 6 p c 7 r e 1 r e 2 a d / i n t 3 s e l c s 0 c s 1 c s 2 r e 1 r e 2 r e 3 r e 5 i n t 3 p o l a d / i n t 3 e l r e 1 r e 2 r e 3 t b 2 0 t b 2 1 b b 2 0 b b 2 1 ? ? ? 0 0 1 6 0 0 1 6 p n 0 0 o c 3 0 o c 3 1 o c 3 2 ? ? 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 7 1 6 ? ? b b 1 7 b b 1 6 b b 1 5b b 1 4 b b 1 3b b 1 2b b 1 1 b b 1 0 t b 1 7t b 1 6 t b 1 5t b 1 4 t b 1 3t b 1 2t b 1 1 t b 1 0 f f 1 6 o c 2 7 o c 2 5o c 2 4 o c 2 3o c 1 2o c 2 1 o c 2 0 o c 3 3 o c 3 4 r e 1 r e 2 r e 3 r e 5 a d / i n t 3 s e l 00 0 0 1 6 ? 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 00 o c 2 6 r c r 0 r c r 1 p n 4 p o l 2p o l 1 o c 3 5 o c 3 6 o c 3 7 s m 6 8 0 1 6 0 0 address register 200 16 pwm0 register (pwm0) 201 16 pwm1 register (pwm1) 202 16 pwm2 register (pwm2) 203 16 pwm3 register (pwm3) 204 16 pwm4 register (pwm4) 205 16 pwm5 register (pwm5) 205 16 pwm6 register (pwm6) 207 16 208 16 209 16 20a 16 20b 16 20c 16 20d 16 20e 16 20f 16 21a 16 21b 16 21c 16 21d 16 21e 16 21f 16 210 16 211 16 212 16 213 16 214 16 215 16 216 16 217 16 218 16 219 16 pwm7 register (pwm7) pwm mode register 1 (pn) pwm mode register 2 (pw) rom correction address 1 (high-order) rom correction address 1 (low-order) rom correction address 2 (high-order) rom correction address 2 (low-order) rom correction enable register (rcr) test register interrupt input polarity register (ip) serial i/o mode register (sm) serial i/o register (sio) osd control register 2(oc2) clock control register (cs) i/o polarity control register (pc) raster color register (rc) osd control register 3(oc3) timer 5 (tm5) timer 6 (tm6) top border control register 1 (tb1) bottom border control register 1 (bb1) top border control register 2 (tb2) bottom border control register 2 (bb2) sfr2 area (addresses 200 16 to 21f 16 ) < bit allocation > function bit no function bit fix to this bit to 0 (do not write to 1 ) fix to this bit to 1 (do not write to 0 ) bit allocation state immediately after reset rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 18 of 170 fig. 8.2.7 memory map of special function register 2 (sfr2) (2) 2 3 0 1 6 2 3 1 1 6 232 16 2 3 3 1 6 2 3 4 1 6 235 16 2 3 6 1 6 2 3 7 1 6 238 16 2 3 9 1 6 2 3 a 1 6 2 3 b 1 6 23c 16 23d 16 2 3 e 1 6 2 3 f 1 6 2 2 0 1 6 221 16 2 2 2 1 6 2 2 3 1 6 2 2 4 1 6 225 16 226 16 2 2 7 1 6 2 2 8 1 6 229 16 2 2 b 1 6 22c 16 2 2 d 1 6 2 2 e 1 6 22f 16 22a 16 v e r t i c a l p o s i t i o n r e g i s t e r 1 1 1 ( v p 1 1 1 ) vertical position register 1 3 (vp1 3 ) vertical position register 1 7 (vp1 7 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 5 ( v p 1 5 ) vertical position register 1 6 (vp1 6 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 1 ( v p 1 1 ) vertical position register 1 2 (vp1 2 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 9 ( v p 1 9 ) vertical position register 1 10 (vp1 10 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 4 ( v p 1 4 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 1 2 ( v p 1 1 2 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 8 ( v p 1 8 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 3 ( v p 2 3 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 7 ( v p 2 7 ) vertical position register 2 5 (vp2 5 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 6 ( v p 2 6 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 1 ( v p 2 1 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 9 ( v p 2 9 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 1 0 ( v p 2 1 0 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 4 ( v p 2 4 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 1 2 ( v p 2 1 2 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 8 ( v p 2 8 ) vertical position register 2 2 (vp2 2 ) vertical position register 2 11 (vp2 11 ) s f r 2 a r e a ( a d d r e s s e s 2 2 0 1 6 t o 2 3 f 1 6 ) a d d r e s sr e g i s t e r bit allocation state immediately after rese t : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : < b i t a l l o c a t i o n > < state immediately after reset > f u n c t i o n b i t : no function bit : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n ame : : 0 immediately after reset : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 v e r t i c a l p o s i t i o n r e g i s t e r 2 1 4 ( v p 2 1 4 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 1 3 ( v p 2 1 3 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 1 6 ( v p 2 1 6 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 1 5 ( v p 2 1 5 ) vertical position register 1 13 (vp1 13 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 1 4 ( v p 1 1 4 ) vertical position register 1 15 (vp1 15 ) vertical position register 1 16 (vp1 16 ) b7 b0 b 7b 0 ? ? ? ? v p 1 1 2 v p 1 1 3 v p 1 1 4 v p 1 1 5 v p 1 1 6 v p 1 1 7 v p 1 2 2 v p 1 2 3 v p 1 2 4 v p 1 2 5 v p 1 2 6 v p 1 2 7 v p 1 3 2 v p 1 3 3 v p 1 3 4 v p 1 3 5 v p 1 3 6 v p 1 3 7 v p 1 4 2 v p 1 4 3 v p 1 4 4 v p 1 4 5 v p 1 4 6 v p 1 4 7 v p 1 5 2 v p 1 5 3 v p 1 5 4 v p 1 5 5 v p 1 5 6 v p 1 5 7 v p 1 6 2 v p 1 6 3 v p 1 6 4 v p 1 6 5 v p 1 6 6 v p 1 6 7 v p 1 7 2 v p 1 7 3 v p 1 7 4 v p 1 7 5 v p 1 7 6 v p 1 7 7 v p 1 8 2 v p 1 8 3 v p 1 8 4 v p 1 8 5 v p 1 8 6 v p 1 8 7 v p 1 9 2 v p 1 9 3 v p 1 9 4 v p 1 9 5 v p 1 9 6 v p 1 9 7 v p 1 1 0 2 v p 1 1 0 3 v p 1 1 0 4 v p 1 1 0 5 v p 1 1 0 6 v p 1 1 0 7 v p 1 1 1 2 v p 1 1 1 3 v p 1 1 1 4 v p 1 1 1 5 v p 1 1 1 6 v p 1 1 1 7 v p 1 1 1 v p 1 2 1 v p 1 3 1 v p 1 4 1 v p 1 5 1 v p 1 6 1 v p 1 7 1 v p 1 8 1 v p 1 9 1 v p 1 1 0 1 v p 1 1 1 1 v p 1 1 2 1 v p 1 1 2 2 v p 1 1 2 3 v p 1 1 2 4 v p 1 1 2 5 v p 1 1 2 6 v p 1 1 2 7 v p 2 1 0 v p 2 1 1 v p 2 2 0 v p 2 2 1 v p 2 3 0 v p 2 3 1 v p 2 4 0 v p 2 4 1 v p 2 5 0 v p 2 5 1 v p 2 6 0 v p 2 6 1 v p 2 7 0 v p 2 7 1 v p 2 8 0 v p 2 8 1 v p 2 9 0 v p 2 9 1 v p 2 1 0 0 v p 2 1 0 1 v p 2 1 1 0 v p 2 1 1 1 v p 2 1 2 0 v p 2 1 2 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? v p 1 1 0 v p 1 2 0 v p 1 3 0 v p 1 4 0 v p 1 5 0 v p 1 6 0 v p 1 7 0 v p 1 8 0 v p 1 9 0 v p 1 1 0 0 v p 1 1 1 0 v p 1 1 2 0 v p 2 1 3 0 v p 2 1 3 1 v p 2 1 4 0 v p 2 1 4 1 v p 2 1 5 0 v p 2 1 5 1 v p 2 1 6 0 v p 2 1 6 1 v p 1 1 4 2 v p 1 1 4 3 v p 1 1 4 4 v p 1 1 4 5 v p 1 1 4 6 v p 1 1 4 7 v p 1 1 5 2 v p 1 1 5 3 v p 1 1 5 4 v p 1 1 5 5 v p 1 1 5 6 v p 1 1 5 7 v p 1 1 6 2 v p 1 1 6 3 v p 1 1 6 4 v p 1 1 6 5 v p 1 1 6 6 v p 1 1 6 7 v p 1 1 4 0 v p 1 1 5 0 v p 1 1 6 0 v p 1 1 4 1 v p 1 1 5 1 v p 1 1 6 1 v p 1 1 3 1 v p 1 1 3 2 v p 1 1 3 3 v p 1 1 3 4 v p 1 1 3 5 v p 1 1 3 6 v p 1 1 3 7v p 1 1 3 0 rev.1.01 2003.07.16 page 19 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.2.8 memory map of special function register 2 (sfr2) (3) sfr2 area (addresses 240 16 to 258 16 ) 250 16 251 16 252 16 253 16 254 16 255 16 256 16 257 16 258 16 240 16 241 16 242 16 243 16 244 16 245 16 246 16 247 16 248 16 249 16 24b 16 24c 16 24d 16 24e 16 24f 16 24a 16 : fix to this bit to 0 (do not write to 1 ) : < bit allocation > < state immediately after reset > function bit : no function bit : fix to this bit to 1 (do not write to 0 ) name : : 0 immediately after reset : indeterminate immediately after reset 0 1 ? : 1 immediately after reset 1 0 address register bit allocation state immediately after reset color pallet register 1 (cr1) color pallet register 2 (cr2) color pallet register 3 (cr3) color pallet register 4 (cr4) color pallet register 5 (cr5) color pallet register 6 (cr6) color pallet register 7 (cr7) color pallet register 9 (cr9) color pallet register10 (cr10) color pallet register 11 (cr11) color pallet register 12 (cr12) color pallet register 13 (cr13) color pallet register 14 (cr14) color pallet register 15 (cr15) left border control register 1 (lb1) left border control register 2 (lb2) right border control register 1 (rb1) right border control register 2 (rb2) sprite vertical position register 1 (vs1) sprite vertical position register 2 (vs2) sprite osd control register (sc) sprite horizontal position register 1 (hs1) sprite horizontal position register 2 (hs2) b7 b0 b7 b0 ? ? ? cr 1 2 cr 1 3 cr 1 4 cr 1 5 cr 1 6 cr 2 2 cr 2 3 cr 2 4 cr 2 5 cr 2 6 cr 3 2 cr 3 3 cr 3 4 cr 3 5 cr 3 6 cr 4 2 cr 4 3 cr 4 4 cr 4 5 cr 4 6 cr 5 2 cr 5 3 cr 5 4 cr 5 5 cr 5 6 cr 6 2 cr 6 3 cr 6 4 cr 6 5 cr 6 6 cr 7 2 cr 7 3 cr 7 4 cr 7 5 cr 7 6 cr 9 2 cr 9 3 cr 9 4 cr 9 5 cr 9 6 cr 10 2 cr 10 3 cr 10 4 cr 10 5 cr 10 6 cr 11 2 cr 11 3 cr 11 4 cr 11 5 cr 11 6 cr 1 1 cr 2 1 cr 3 1 cr 4 1 cr 5 1 cr 6 1 cr 7 1 cr 9 1 cr 10 1 cr 11 1 cr 12 1 cr 12 2 cr 12 3 cr 12 4 cr 12 5 cr 12 6 lb10 lb11 vs10 vs11 vs20 vs21 hs10 hs11 hs20 hs21 sc0 sc1 ? ? ? ? ? ? ? ? ? ? ? ? 07 16 ff 16 ? 00 16 00 16 cr 1 0 cr 2 0 cr 3 0 cr 4 0 cr 5 0 cr 6 0 cr 7 0 cr 9 0 cr 10 0 cr 11 0 cr 12 0 cr 14 2 cr 14 3 cr 14 4 cr 14 5 cr 14 6 cr 15 2 cr 15 3 cr 15 4 cr 15 5 cr 15 6 cr 14 0 cr 15 0 cr 14 1 cr 15 1 cr 13 1 cr 13 2 cr 13 3 cr 13 4 cr 13 5 cr 13 6cr 13 0 lb12 lb13 lb14 lb15 lb16 lb17 lb20 lb21 lb22 rb10 rb11 rb12 rb13 rb14 rb15 rb16 rb17 rb20 rb21 rb22 vs12 vs13 vs14 vs15 vs16 vs17 hs12 hs13 hs14 hs15 hs16 hs17 hs22 sc2 sc3 sc4 sc5 ? 00 16 01 16 ? ? ? ? 0 0 0 0 0 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 20 of 170 fig. 8.2.9 internal state of processor status register and program counter at reset b 7 b 0 b 7 b 0 1 register p r o c e s s o r s t a t u s r e g i s t e r ( p s ) bit allocation state immediately after reset p r o g r a m c o u n t e r ( p c h ) p r o g r a m c o u n t e r ( p c l ) c o n t e n t s o f a d d r e s s f f f f 1 6 c o n t e n t s o f a d d r e s s f f f e 1 6 i zc d b t v n?? ? ? ? ? ? : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : < b i t a l l o c a t i o n > < s t a t e i m m e d i a t e l y a f t e r r e s e t > f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 rev.1.01 2003.07.16 page 21 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 8.3 interrupts interrupts can be caused by 19 different sources consisting of 3 ex- ternal, 14 internal, 1 software, and reset. interrupts are vectored in- terrupts with priorities as shown in table 8.3.1. reset is also included in the table because its operation is similar to an interrupt. when an interrupt is accepted, the contents of the program counter and processor status register are automatically stored into the stack. ? the interrupt disable flag i is set to 1 and the corresponding interrupt request bit is set to 0. ? the jump destination address stored in the vector address enters the program counter. nothing to stop reset. other interrupts are disabled when the interrupt disable flag is set to 1. all interrupts except the brk instruction interrupt have an interrupt request bit and an interrupt enable bit. the interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. figures 8.3.2 to 8.3.6 show the interrupt-related registers. interrupts other than the brk instruction interrupt and reset are ac- cepted when the interrupt enable bit is 1, interrupt request bit is 1, and the interrupt disable flag is 0. the interrupt request bit can be set to 0 by a program, but not set to 1. the interrupt enable bit can be set to 0 and 1 by a program. reset is treated as a non-maskable interrupt with the highest priority. figure 8.3.1 shows interrupt control. 8.3.1 interrupt causes (1) v sync and osd interrupts the v sync interrupt is an interrupt request synchronized with the vertical sync signal. the osd interrupt occurs after character block display to the crt is completed. (2) int1, int2 external interrupts the int1 and int2 interrupts are external interrupt inputs, the system detects that the level of a pin changes from low to high or from high to low, and generates an interrupt request. the input active edge can be selected by bits 3 and 4 of the interrupt input polarity register (address 0212 16 ) : when this bit is 0, a change from low to high is detected; when it is 1, a change from high to low is detected. note that both bits are cleared to 0 at reset. (3) timer 1 to 4 interrupts an interrupt is generated by an overflow of timer 1, 2, 3 or 4. vector addresses ffff 16 , fffe 16 fffd 16 , fffc 16 fffb 16 , fffa 16 fff9 16 , fff8 16 fff7 16 , fff6 16 fff5 16 , fff4 16 fff3 16 , fff2 16 fff1 16 , fff0 16 ffef 16 , ffee 16 ffed 16 , ffec 16 ffeb 16 , ffea 16 ffe9 16 , ffe8 16 ffe7 16 , ffe6 16 ffe5 16 , ffe4 16 ffe3 16 , ffe2 16 ffdf 16 , ffde 16 interrupt source reset osd interrupt int1 external interrupt data slicer interrupt serial i/o interrupt timer 4 interrupt f(x in )/4096 sprite osd interrupt v sync interrupt timer 3 interrupt timer 2 interrupt timer 1 interrupt a-d convertion int3 external interrupt int2 external interrupt multi-master i 2 c-bus interface interrupt timer 5 6 interrupt brk instruction interrupt remarks non-maskable active edge selectable software switch by software (see note) software switch by software (see note)/ when selecting int3 interrupt, active edge selectable. active edge selectable software switch by software (see note) non-maskable (software interrupt) table 8.3.1 interrupt vector addresses and priority priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 note : switching a source during a program causes an unnecessary interrupt occurs. accordingly, set a source at initializing of progr am. m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 22 of 170 (4) serial i/o interrupt this is an interrupt request from the clock synchronous serial i/o function. (5) f(x in )/4096 ?sprite osd interrupt the f (x in )/4096 interrupt occurs regularly with a f(x in )/4096 pe- riod. set bit 0 of the pwm mode register 1 to 0. the sprite osd interrupt occurs at the completion of sprite display. since f(x in )/4096 interrupt and sprite osd interrupt share the same vector, an interrupt source is selected by bit 5 of the sprite osd control register (address 0258 16 ). (6) data slicer interrupt an interrupt occurs when slicing data is completed. (7) multi-master i 2 c-bus interface interrupt this is an interrupt request related to the multi-master i 2 c-bus interface. (8) a-d conversion ?int3 external interrupt the a-d conversion interrupt occurs at the completion of a-d conversion. the int3 is an external input,the system detects that the level of a pin changes from low to high or from high to low, and generates an interrupt request. the input active edge can be selected by bit 6 of the interrupt input polarity register (address 0212 16 ) : when this bit is 0, a change from low to high is detected; when it is 1, a change from high to low is detected. note that this bit is cleared to 0 at reset. since a-d conversion interrupt and the int3 external interrupt share the same vector, an interrupt source is selected by bit 7 of the interrupt interval determination control register (address 0212 16 ). (9) timer 5 ?6 interrupt an interrupt is generated by an overflow of timer 5 or 6. their priorities are same, and can be switched by software. (10) brk instruction interrupt this software interrupt has the least significant priority. it does not have a corresponding interrupt enable bit, and it is not af- fected by the interrupt disable flag i (non-maskable). fig. 8.3.1 interrupt control interrupt request bi t interrupt enable bi t interrupt disable flag i brk instruction reset interrupt request rev.1.01 2003.07.16 page 23 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.3.2 interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 1 (ireq1) [address 00fc b name interrupt request register 1 0 timer 1 interrupt re q uest bit ( tm1r ) 1 timer 2 interrupt re q uest bit ( tm2r ) 2 timer 3 interrupt re q uest bit ( tm3r ) 3 timer 4 interrupt re q uest bit ( tm4r ) 4 osd interrupt request bit ( osdr ) 5v sync interrupt re q uest bit ( vscr ) 6 a-d conversion int3 external interrupt request bit ( adr ) 7 ? : 0 can be set by software, but 1 cannot be set. 16 ] functions 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued after reset rw 0 0 ? 0 ? 0 ? ? 0 ? 0 ? 0 ? r r r r r r r r nothing is assigned. this bit is a write disable bit. when this bit is read out , the value is 0. 0 fig. 8.3.3 interrupt request register 2 b7 b 6 b5 b4 b3 b2 b1 b0 interrupt request register 2 (ireq2) [address 00fd b name interrupt request register 2 0 int1 external interrupt re q uest bit ( in1r ) 1 data slicer interrupt re q uest bit ( dsr ) 2 serial i/o interrupt re q uest bit ( sior ) 3 4 int2 external interrupt request bit ( in2r ) 5 7 fix this bit to 0. 0 ? : 0 can be set by software, but 1 cannot be set. 16 ] f(x in )/4096 sprite osd interru p t re q uest bit ( ckr ) multi-master i 2 c-bus interrupt re q uest bit ( iicr ) 6 timer 5 6 interrupt request bit (tm56r) functions 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued after reset 0 0 0 0 0 0 0 0 rw ? ? ? ? r r r r ? ? ? r m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 24 of 170 fig. 8.3.4 interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 1 (icon1) [address 00fe 16 ] b 0 na me interrupt control register 1 timer 1 interrupt enable bit (tm1e) 1 timer 2 interrupt enable bit (tm2e) 2 timer 3 interrupt enable bit (tm3e) 3 4 osd interrupt enable bit (osde) 7 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. timer 4 interrupt enable bit (tm4e) 5v sync interrupt enable bit (vsce) 6 a-d conversion int3 external interrupt enable bit (ade) functions 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enable d after reset 0 0 0 0 0 0 0 0 rw rw rw rw rw rw r rw rw fig. 8.3.5 interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 2 (icon2) [address 00ff 16 ] b name functions after reset interrupt control register 2 0 int1 external interrupt enable bit ( in1e ) 0 : interrupt disabled 1 : interrupt enabled 1 data slicer interrupt enable bit ( dse ) 2 serial i/o interrupt enable bit ( sioe ) 3 4 int2 external interrupt enable bit ( in2e ) 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 0 0 0 0 f(x in )/4096 sprite osd interrupt enable bit (cke) 0 : interrupt disabled 1 : interrupt enabled 5 multi-master i 2 c-bus interface interrupt enable bit (iice) 0 : interrupt disabled 1 : interrupt enabled 0 6 timer 5 6 interrupt enable bit ( tm56e ) 0 : interrupt disabled 1 : interrupt enabled 0 7 timer 5 6 interrupt switch bit ( tm56s ) 0 : timer 5 1 : timer 6 0 rw rw rw rw rw rw rw rw rw rev.1.01 2003.07.16 page 25 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.3.6 interrupt input polarity register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( i p ) [ a d d r e s s 0 2 1 2 1 6 ] b n am e f unct i on s a f t e r r e s e t r w i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r 0 0 t o 2 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . r ? i n t 1 p o l a r i t y s w i t c h b i t ( p o l 1 ) 0 0 3 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 4 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 6 i n t 2 p o l a r i t y s w i t c h b i t ( p o l 2 ) i n t 3 p o l a r i t y s w i t c h b i t ( p o l 3 ) r w r w r w 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 0 : i n t 3 i n t e r r u p t 1 : a - d c o n v e r s i o n i n t e r r u p t 7 a - d convers i on int 3 interrupt source selection bit (ad/int3sel) r w 0 5 n o t h i n g i s a s s i g n e d . t h i s b i t i s w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . r ? 0 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 26 of 170 8.4 timers this microcomputer has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. all timers are 8-bit timers with the 8-bit timer latch. the timer block diagram is shown in figure 8.4.3. all of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. by writing a count value to the correspond- ing timer latch (addresses 00f0 16 to 00f3 16 : timers 1 to 4, addresses 021a 16 and 021b 16 : timers 5 and 6), the value is also set to a timer, simultaneously. down counts ?n 16 ?1, nn 16 ?2......., 01 16 , 00 16 ?by the input of the count source from the right after setting to the timer. the interrupt is requested by a timer overflow at the next count source input in which the value of the timer becomes ?0 16 . each timers are explained below. 8.4.1 timer 1 timer 1 can select one of the following count sources: f(x in )/16 or f(x cin )/16 f(x in )/4096 or f(x cin )/4096 external clock from the tim2 pin the count source of timer 1 is selected by setting bits 5 and 0 of timer mode register 1 (address 00f4 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. timer 1 interrupt request occurs at timer 1 overflow. 8.4.2 timer 2 timer 2 can select one of the following count sources: f(x in )/16 or f(x cin )/16 timer 1 overflow signal external clock from the tim2 pin the count source of timer 2 is selected by setting bits 4 and 1 of timer mode register 1 (address 00f4 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. when timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8- bit prescaler. timer 2 interrupt request occurs at timer 2 overflow. 8.4.3 timer 3 timer 3 can select one of the following count sources: f(x in )/16 or f(x cin )/16 f(x cin ) external clock from the tim3 pin the count source of timer 3 is selected by setting bit 0 of timer mode register 2 (address 00f5 16 ) and bit 6 at address 00c7 16 . either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. timer 3 interrupt request occurs at timer 3 overflow. 8.4.4 timer 4 timer 4 can select one of the following count sources: f(x in )/16 or f(x cin )/16 f(x in )/2 or f(x cin )/2 f(x cin ) timer 3 overflow signal the count source of timer 4 is selected by setting bits 1 and 4 of timer mode register 2 (address 00f5 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. when timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8- bit prescaler. timer 4 interrupt request occurs at timer 4 overflow. 8.4.5 timer 5 timer 5 can select one of the following count sources: f(x in )/16 or f(x cin )/16 timer 2 overflow signal timer 4 overflow signal the count source of timer 5 is selected by setting bit 6 of timer mode register 1 (address 00f4 16 ) and bit 7 of timer mode register 2 (ad- dress 00f5 16 ). when overflow of timer 2 or 4 is a count source for timer 5, either timer 2 or 4 functions as an 8-bit prescaler. either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. timer 5 interrupt request occurs at timer 5 overflow. 8.4.6 timer 6 timer 6 can select one of the following count sources: f(x in )/16 or f(x cin )/16 timer 5 overflow signal the count source of timer 6 is selected by setting bit 7 of timer mode register 1 (address 00f4 16 ). either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. when timer 5 overflow signal is a count source for timer 6, timer 5 functions as an 8-bit prescaler. timer 6 interrupt request occurs at timer 6 overflow. at reset, timers 3 and 4 are connected by hardware and ?f 16 ?is automatically set in timer 3; ?7 16 ?in timer 4. the f(x in ) ? /16 is se- lected as the timer 3 count source. the internal reset is released by timer 4 overflow in this state and the internal clock is connected. at execution of the stp instruction, timers 3 and 4 are connected by hardware and ?f 16 ?is automatically set in timer 3; ?7 16 ?in timer 4. however, the f(x in ) ? /16 is not selected as the timer 3 count source. so set both bit 0 of timer mode register 2 (address 00f5 16 ) and bit 6 at address 00c7 16 to ??before execution of the stp instruction (f(x in ) ? /16 is selected as the timer 3 count source). the internal stp state is released by timer 4 overflow in this state and the inter- nal clock is connected. as a result of the above procedure, the program can start under a stable clock. ? : when bit 7 of the cpu mode register (cm7) is ?,?f(x in ) be- comes f(x cin ). the timer-related registers is shown in figures 8.4.1 and 8.4.2. rev.1.01 2003.07.16 page 27 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp fig. 8.4.1 timer mode register 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 timer mode register 1 (tm1) [address 00f4 16 ] b after reset w t i m e r m o d e r e g i s t e r 1 0 1 2 3 4 n a m e functions t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t 1 ( t m 1 0 ) 0: f(x in )/16 or f(x cin )/16 (see note) 1: count source selected by bit 5 of tm1 t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t 1 ( t m 1 1 ) 0: count source selected by bit 4 of tm1 1: external clock from tim2 pin t i m e r 1 c o u n t s t o p b i t ( t m 1 2 ) 0: count start 1: count stop timer 2 count stop bit (tm13) 0: count start 1: count stop t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t 2 ( t m 1 4 ) r 0 0 0 0 0 w r w r w r w r w r 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 1 overflow 5 timer 1 count source selection bit 2 (tm15) 0: f(x in )/4096 or f(x cin )/4096 (see note) 1: external clock from tim2 pin 0w r 6 t i m e r 5 c o u n t s o u r c e s e l e c t i o n b i t 2 ( t m 1 6 ) 0: timer 2 overflow 1: timer 4 overflow 0w r 7 t i m e r 6 c o u n t s o u r c e s e l e c t i o n b i t ( t m 1 7 ) 0w r 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 5 overflow n o t e : e i t h e r f ( x i n ) o r f ( x c i n ) i s s e l e c t e d b y b i t 7 o f t h e c p u m o d e r e g i s t e r . m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 28 of 170 fig. 8.4.2 timer mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 2 (tm2) [address 00f5 16 ] b after reset r w timer mode register 2 0 name functions timer 3 count source selection bit (tm20) 0 rw 1, 4 timer 4 count source selection bits (tm21, tm24) 0 rw 2 3 0 timer 3 count stop bit (tm22) 0: count start 1: count stop timer 4 count stop bit (tm23) 0: count start 1: count stop 0 0 5 timer 5 count stop bit (tm25) 0: count start 1: count stop 0 6 timer 6 count stop bit (tm26) 0: count start 1: count stop 0 rw rw rw rw r w 7 timer 5 count source selection bit 1 (tm27) 0: f(x in )/16 or f(x cin )/16 (see note) 1: count source selected by bit 6 of tm1 b0 0 0 : f(x in )/16 or f(x cin )/16 (see note) 1 0 : f(x cin ) 01: 11 : (b6 at address 00c7 16 ) external clock from tim3 pin b4 b1 0 0 : timer 3 overflow signal 0 1 : f(x in )/16 or f(x cin )/16 (see note) 1 0 : f(x in )/2 or f(x cin )/2 (see note) 1 1 : f(x cin ) note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. rev.1.01 2003.07.16 page 29 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.4.3 timer block diagram t i m e r 1 ( 8 ) 1 / 4 0 9 6 1 / 2 cm7 t m 1 5 1 / 8 t i m e r 1 l a t c h ( 8 ) 8 8 8 tm10 t m 1 2 t m 1 4 t m 1 1 tm1 3 timer 2 (8) timer 2 latch (8) 8 8 8 timer 3 (8) t i m e r 3 l a t c h ( 8 ) 8 8 8 timer 4 (8) t i m e r 4 l a t c h ( 8 ) 8 8 8 t i m e r 5 ( 8 ) t i m e r 5 l a t c h ( 8 ) 8 8 8 t i m e r 6 ( 8 ) timer 6 latch (8) 8 8 8 d a t a b u s t i m e r 1 i n t e r r u p t r e q u e s t t i m e r 2 i n t e r r u p t r e q u e s t t i m e r 3 i n t e r r u p t r e q u e s t reset stp instruction t m 2 0 t m 2 2 t3cs t i m e r 4 i n t e r r u p t r e q u e s t t m 2 4 tm23 t m 2 1 tm16 t i m e r 5 i n t e r r u p t r e q u e s t t m 2 7 tm25 t i m e r 6 i n t e r r u p t r e q u e s t t m 1 7 tm26 tm21 x c i n x i n t i m 2 t i m 3 s e l e c t i o n g a t e :c o n n e c t e d t o b l a c k s i d e a t r e s e t t m 1 : t i m e r m o d e r e g i s t e r 1 t m 2 : t i m e r m o d e r e g i s t e r 2 t 3 c s : t i m e r 3 c o u n t s o u r c e s w i t c h b i t ( a d d r e s s 0 0 c 7 1 6 ) c m : c p u m o d e r e g i s t e r n o t e s 1 : h i g h p u l s e w i d t h o f e x t e r n a l c l o c k i n p u t s t i m 2 a n d t i m 3 n e e d s 4 m a c h i n e c y c l e s o r m o r e . 2 : w h e n t h e e x t e r n a l c l o c k s o u r c e i s s e l e c t e d , t i m e r s 1 , 2 , a n d 3 a r e c o u n t e d a t a r i s i n g e d g e o f i n p u t s i g n a l . f f 1 6 0 7 1 6 3 : i n t h e s t o p m o d e o r t h e w a i t m o d e , e x t e r n a l c l o c k i n p u t s t i m 2 a n d t i m 3 c a n n o t b e u s e d . m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 30 of 170 8.5 serial i/o this microcomputer has a built-in serial i/o which can either transmit or receive 8-bit data serially in the clock synchronous mode. the serial i/o block diagram is shown in figure 8.5.1. the synchro- nous clock i/o pin (s clk ), and data output pin (s out ) also function as port p4, data input pin (s in ) also functions as ports p1 and p7. bit 2 of the serial i/o mode register (address 0213 16 ) selects whether the synchronous clock is supplied internally or externally (from the s clk pin). when an internal clock is selected, bits 1 and 0 select whether f(x in ) or f(x cin ) is divided by 8, 16, 32, or 64. to use the pin for servial i/o, set the bit corresponding to s clk pin of thr port p4 direction register (address 00c9 16 ) and the bit corresponding to s in pin of the port p1 direction register (address 00c3 16 ) to 0 . fig. 8.5.1 serial i/o block diagram 8 serial i/o shift register (8) data bus serial i/o interrupt request selection g ate: connect to black side at reset. synchronous circuit frequency divider 1/8 1/4 1/16 sm1 sm0 serial i/o counter (8) sm5 : lsb msb sm2 1/2 x in s in s out s clk 1/2 (address 0214 16 ) x cin 1/2 cm7 1/2 note : when the data is set in the serial i/o register (address 0214 16 ), the register functions as the serial i/o shift register. (note) cm : cpu mode register sm : serial i/o mode register more over, set the bit corresponding to s out of rhe port p4 direction register (address 00c9 16 ) to 1 and, to use s out pin for serial i/o, set the corresponding bits of the port p4 direction register (address 00c9 16 ) to 1. the operation of the serial i/o is described below. the operation of the serial i/o differs depending on the clock source; external clock or internal clock. rev.1.01 2003.07.16 page 31 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.5.2 serial i/o timing (for lsb first) synchronous cloc k transfer clock serial i/o register write signal serial i/o output s out d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 (note) serial i/o input s in note : when an internal clock is selected, the s out pin is at high-impedance after transfer is completed. interrupt request bit is set to 1 internal clock : the serial i/o counter is set to 7 during the write cycle into the serial i/o register (address 0214 16 ), and the transfer clock goes h forcibly. at each falling edge of the transfer clock after the write cycle, serial data is output from the s out pin. transfer di- rection can be selected by bit 5 of the serial i/o mode register. at each rising edge of the transfer clock, data is input from the s in pin and data in the serial i/o register is shifted 1 bit. after the transfer clock has counted 8 times, the serial i/o counter becomes 0 and the transfer clock stops at high. at this time the interrupt request bit is set to 1. external clock : the an external clock is selected as the clock source, the interrupt request is set to 1 after the transfer clock has been counted 8 counts. however, transfer operation does not stop, so the clock should be controlled externally. use the external clock of 500 khz or less with a duty cycle of 50 %. the serial i/o timing is shown in figure 8.5.2. when using an exter- nal clock for transfer, the external clock must be held at high for initializing the serial i/o counter. when switching between an inter- nal clock and an external clock, do not switch during transfer. also, be sure to initialize the serial i/o counter after switching. notes 1: on programming, note that the serial i/o counter is set by writing to the serial i/o register with the bit managing instructions, such as seb and clb. 2: when an external clock is used as the synchronous clock, write trans- mit data to the serial i/o register when the transfer clock input level is high. m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 32 of 170 fig. 8.5.3 serial i/o mode register b 7 b 6 b 5 b 4 b3 b 2 b 1 b 0 serial i/o mode register (sm) [address 0213 16 ] bn a m ef u n c t i o n s a f t e r r e s e t rw s e r i a l i / o m o d e r e g i s t e r 0 , 1 internal synchronous clock selection bits (sm0, sm1) b 1 b 0 0 0 : f ( x i n ) / 8 o r f ( x c i n ) / 8 0 1 : f ( x i n ) / 1 6 o r f ( x c i n ) / 1 6 1 0 : f ( x i n ) / 3 2 o r f ( x c i n ) / 3 2 1 1 : f ( x i n ) / 6 4 o r f ( x c i n ) / 6 4 2 synchronous clock selection bit (sm2) 3 port function selection bit (sm3) 6 5 transfer direction selection bit (sm5) 0 : p 1 1 , p 1 3 1 : s c l 1 , s d a 1 0 : e x t e r n a l c l o c k 1 : i n t e r n a l c l o c k 0 : t r a n s f e r f r o m t h e l a s t s i g n i f i c a n t b i t ( l s b ) 1 : t r a n s f e r f r o m t h e t o p s i g n i f i c a n t b i t ( m s b ) 0 0 0 0 0 0 rw rw rw r w rw rw 4 port function selection bit (sm4) 0 : p 1 2 , p 1 4 1 : s c l 2 , s d a 2 7 n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . 0r s in pin switch bit (sm6) 0: p1 7 is s in pin 1: p7 2 is s in pin rev.1.01 2003.07.16 page 33 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at = 4 mhz) table 8.6.1 multi-master i 2 c-bus interface functions item format communication mode scl clock frequency : system clock = f(x in )/2 note : we are not responsible for any third party s infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the i 2 c control register at address 00f9 16 ) for connections between the i 2 c-bus interface and ports (scl1, scl2, sda1, sda2). 8.6 multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communications cir- cuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. figure 8.6.1 shows a block diagram of the multi-master i 2 c-bus in- terface and table 8.6.1 shows multi-master i 2 c-bus interface func- tions. this multi-master i 2 c-bus interface consists of the i 2 c address reg- ister, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register and other control circuits. fig. 8.6.1 block diagram of multi-master i 2 c-bus interface i 2 c address register (s0d) b 7b 0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw n o i s e e l i m i n a t i o n c i r c u i t s e r i a l d a t a ( s d a ) add ress comparator b7 i c d ata s hif t reg i ster b 0 d a t a c o n t r o l c i r c u i t i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) s y s t e m c l o c k ( ) i nterrupt generating circuit i nterrupt request signal (iicirq) b7 m s t trx b b pin a l aas ad 0 l r b b0 i c s t a t u s r e g i s t e r ( s 1 ) b 7b 0 bsel1 bsel0 1 0 b i t s a d als b c 2b c 1bc0 i 2 c c o n t r o l r e g i s t e r ( s 1 d ) bi t counter b b c i r c u i t c l o c k c o n t r o l c i r c u i t n o i s e e l i m i n a t i o n c i r c u i t s e r i a l c l o c k ( s c l ) b 7b0 ack a c k b i t fast mode ccr4 ccr3 ccr2 ccr1 ccr0 i nterna l d ata b us c l o c k d i v i s i o n s 0 al circuit e s o 2 2 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 34 of 170 8.6.1 i 2 c data shift register the i 2 c data shift register (s0 : address 00f6 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. the i 2 c data shift register is in a write enable status only when the eso bit of the i 2 c control register (address 00f9 16 ) is ?.?the bit counter is reset by a write instruction to the i 2 c data shift register. when both the eso bit and the mst bit of the i 2 c status register (address 00f8 16 ) are ?,?the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift regis- ter is always enabled regardless of the eso bit value. note: to write data into the i 2 c data shift register after setting the mst bit to ??(slave mode), keep an interval of 8 machine cycles or more. fig. 8.6.2 data shift register b7 b6 b5 b4 b3 b2 b1 b0 i 2 c data shift register (s0) [address 00f6 16 ] b functions after reset r w i 2 c data shift register 0 to 7 this is an 8-bit shift register to store receive data and write transmit data. indeterminate note: to write data into the i 2 c data shift register after setting the mst bit to ??(slave mode), keep an interval of 8 machine cycles or more. name d0 to d7 rw rev.1.01 2003.07.16 page 35 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp 8.6.2 i 2 c address register the i 2 c address register (address 00f7 16 ) consists of a 7-bit slave address and a read/write bit. in the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the start condition are detected. (1) bit 0: read/write bit (rbw) not used when comparing addresses, in the 7-bit addressing mode. in the 10-bit addressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rbw) of the i 2 c address register. the rbw bit is cleared to ??automatically when the stop condi- tion is detected. (2) bits 1 to 7: slave address (sad0?ad6) these bits store slave addresses. regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. fig. 8.6.3 i 2 c address register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 r e a d / w r i t e b i t ( r b w ) 1 t o 7 s l a v e a d d r e s s ( s a d 0 t o s a d 6 ) < o n l y i n 1 0 - b i t a d d r e s s i n g ( i n s l a v e ) m o d e > t h e l a s t s i g n i f i c a n t b i t o f a d d r e s s d a t a i s c o m p a r e d . 0 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r s t a r t c o n d i t i o n ( r e a d s t a t e ) 1 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r r e s t a r t c o n d i t i o n ( w r i t e s t a t e ) < i n b o t h m o d e s > t h e a d d r e s s d a t a i s c o m p a r e d . i 2 c a d d r e s s r e g i s t e r i 2 c a d d r e s s r e g i s t e r ( s 0 d ) [ a d d r e s s 0 0 f 7 1 6 ] b n a m e f u n c t i o n s 0 0 a f t e r r e s e t r w r r w m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 36 of 170 8.6.3 i 2 c clock control register the i 2 c clock control register (address 00fa 16 ) is used to set ack control, scl mode and scl frequency. (1) bits 0 to 4: scl frequency control bits (ccr0?cr4) these bits control the scl frequency. (2) bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to ?,?the stan- dard clock mode is set. when the bit is set to ?,? the high-speed clock mode is set. (3) bit 6: ack bit (ack bit) this bit sets the sda status when an ack clock ? is generated. when this bit is set to ?,?the ack return mode is set and sda goes to low at the occurrence of an ack clock. when the bit is set to ?, the ack non-return mode is set. the sda is held in the high status at the occurrence of an ack clock. however, when the slave address matches the address data in the reception of address data at ack bit = ?,? the sda is automatically made low (ack is returned). if there is a mismatch between the slave address and the address data, the sda is automatically made high (ack is not returned). ? ack clock: clock for acknowledgement fig. 8.6.4 i 2 c clock control (4) bit 7: ack clock bit (ack) this bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. when this bit is set to ?, the no ack clock mode is set. in this case, no ack clock occurs after data transmission. when the bit is set to ?,?the ack clock mode is set and the master generates an ack clock upon comple- tion of each 1-byte data transmission.the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (make sda high) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 c clock control register during transmission. if data is written during transmission, the i 2 c clock generator is reset, so that data cannot be transmitted normally. b7 b6 b5 b4 b3 b2 b1 b0 i 2 c clock control register (s2) [address 00fa 16 ] i 2 c clock control register 0 to 4 scl frequency control bits (ccr0 to ccr4) 7 5 6 scl mode specification bit (fast mode) 0: standard clock mode 1: high-speed clock mode 0 standard clock mode b name function s after reset r w 0 0 0 ack bit (ack bit) ack clock bit (ack) 0: ack is returned. 1: ack is not returned. 0: no ack clock 1: ack clock high speed clock mode setup disabled setup disabled 00 to 02 333 03 250 04 100 400 (see note) 05 83.3 166 06 500/ccr value 1000/ccr value ... 17.2 34.5 1d 16.6 33.3 1e 16.1 32.3 1f note: at 400 khz in the high-speed clock mode, the duty is as below . 0 period : 1 period = 3 : 2 in the other cases, the duty is as below. 0 period : 1 period = 1 : 1 register value b4 to b0 r w r w r w r w (at f = 4 mhz, unit : khz) setup disabled setup disabled rev.1.01 2003.07.16 page 37 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp 8.6.4 i 2 c control register the i 2 c control register (address 00f9 16 ) controls the data commu- nication format. (1) bits 0 to 2: bit counter (bc0 bc2) these bits decide the number of bits for the next 1-byte data to be transmitted. an interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. when a start condition is received, these bits become ?00 2 ?and the address data is always transmitted and received in 8 bits. (2) bit 3: i 2 c interface use enable bit (eso) this bit enables usage of the multimaster i 2 c bus interface. when this bit is set to ?,?the use disable status is provided, so the sda and the scl become high-impedance. when the bit is set to ?,?use of the interface is enabled. when eso = ?,?the following is performed. pin = ?,?bb = ??and al = ??are set (they are bits of the i 2 c status register at address 00f8 16 ). writing data to the i 2 c data shift register (address 00f6 16 ) is dis- abled. (3) bit 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to ?,?the addressing format is selected, so that ad- dress data is recognized. when a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to ?.6.5 i 2 c status register,?bit 1) is received, trans- mission processing can be performed. when this bit is set to ?,?the free data format is selected, so that slave addresses are not recog- nized. (4) bit 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to ?,?the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address register (ad- dress 00f7 16 ) are compared with address data. when this bit is set to ?,?the 10-bit addressing format is selected, all the bits of the i 2 c address register are compared with address data. (5) bits 6 and 7:connection control bits between i 2 c-bus interface and ports (bsel0, bsel1) these bits controls the connection between scl and ports or sda and ports (refer to figure 8.6.5). fig. 8.6.5 connection port control by bsel0 and bsel1 note: when using multi-master i 2 c-bus interface, set bits 3 and 4 of the serial i/o mode register (address 0213 16 ) to ?. moreover, set the corresponding direction register to ??to use the port as multi-master i 2 c-bus interface. 0 1 bsel0 scl1/p1 1 scl2/p1 2 0 1 bsel1 0 1 bsel0 sda1/p1 3 sda2/p1 4 0 1 bsel1 multi-master i 2 c-bus interface scl sda m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 38 of 170 fig. 8.6.6 i 2 c control register b7 b6 b5 b4 b3 b2 b1 b0 0 to 2 bit counter (number of transmit/recieve bits) (bc0 to bc2) b2 b1 b0 0 0 0: 8 0 0 1: 7 0 1 0: 6 0 1 1: 5 1 0 0: 4 1 0 1: 3 1 1 0: 2 1 1 1: 1 3i 2 c-bus interface use enable bit (eso) 0: disabled 1: enabled 4 data format selection bit (als) 0: addressing format 1: free data format 5 addressing format selection bit (10bit sad) 0: 7-bit addressing format 1: 10-bit addressing format 6, 7 connection control bits between i 2 c-bus interface and ports (bsel0, bsel1) b7 b6 connection port (see note) 0 0: none 0 1: scl1, sda1 1 0: scl2, sda2 1 1: scl1, sda1, scl2, sda2 0 0 0 0 0 i 2 c control register (s1d) [address 00f9 16 ] i 2 c control register b name function s after reset r w r w r w r w r w r w rev.1.01 2003.07.16 page 39 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp 8.6.5 i 2 c status register the i 2 c status register (address 00f8 16 ) controls the i 2 c-bus inter- face status. the low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. (1) bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to ?.?if ack is not returned, this bit is set to ?.? except in the ack mode, the last bit value of received data is input. the state of this bit is changed from ??to ??by executing a write instruction to the i 2 c data shift register (address 00f6 16 ). (2) bit 1: general call detecting flag (ad0) this bit is set to ??when a general call ? whose address data is all ??is received in the slave mode. by a general call of the master device, every slave device receives control data after the general call. the ad0 bit is set to ??by detecting the stop condition or start condition. ? general call: the master transmits the general call address ?0 16 to all slaves. (3) bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data. in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to ??in one of the following conditions. the address data immediately after occurrence of a start con- dition matches the slave address stored in the high-order 7 bits of the i 2 c address register (address 00f7 16 ). a general call is received. in the slave reception mode, when the 10-bit addressing format is selected, this bit is set to ??with the following condition. when the address data is compared with the i 2 c address regis- ter (8 bits consists of slave address and rbw), the first bytes match. the state of this bit is changed from ??to ??by executing a write instruction to the i 2 c data shift register (address 00f6 16 ). (4) bit 3: arbitration lost ? detecting flag (al) in the master transmission mode, when a device other than the mi- crocomputer sets the sda to ?,? arbitration is judged to have been lost, so that this bit is set to ?.?at the same time, the trx bit is set to ?,?so that immediately after transmission of the byte whose arbitra- tion was lost is completed, the mst bit is set to ?.?when arbitration is lost during slave address transmission, the trx bit is set to ??and the reception mode is set. consequently, it becomes possible to re- ceive and recognize its own slave address transmitted by another master device. ? arbitration lost: the status in which communication as a master is disabled. (5) bit 4: i 2 c-bus interface interrupt request bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the state of the pin bit changes from ??to ?.?at the same time, an interrupt request signal is sent to the cpu. the pin bit is set to ??in synchronization with a falling edge of the last clock (including the ack clock) of an internal clock and an interrupt re- quest signal occurs in synchronization with a falling edge of the pin bit. when the pin bit is ?,?the scl is kept in the ??state and clock generation is disabled. figure 8.6.8 shows an interrupt request sig- nal generating timing chart. the pin bit is set to ??in any one of the following conditions. executing a write instruction to the i 2 c data shift register (address 00f6 16 ). when the eso bit is ? at reset the conditions in which the pin bit is set to ??are shown below: immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) immediately after completion of 1-byte data reception in the slave reception mode, with als = ??and immediately after completion of slave address or general call address reception in the slave reception mode, with als = ??and immediately after completion of address data reception (6) bit 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to ?,?this bus system is not busy and a start condition can be generated. when this bit is set to ?,?this bus system is busy and the occurrence of a start condition is disabled by the start condition duplication prevention function (note). this flag can be written by software only in the master transmission mode. in the other modes, this bit is set to ??by detecting a start condition and set to ??by detecting a stop condition. when the eso bit of the i 2 c control register (address 00f9 16 ) is ??and at reset, the bb flag is kept in the ??state. (7) bit 6: communication mode specification bit (transfer direc- tion specification bit: trx) this bit decides the direction of transfer for data communication. when this bit is ?,?the reception mode is selected and the data of a trans- mitting device is received. when the bit is ?,?the transmission mode is selected and address data and control data are output into the sda in synchronization with the clock generated on the scl. when the als bit of the i 2 c control register (address 00f9 16 ) is ??in the slave reception mode is selected, the trx bit is set to ??(trans- __ mit) if the least significant bit (r/w bit) of the address data transmit- __ ted by the master is ?.?when the als bit is ??and the r/w bit is ?,?the trx bit is cleared to ?? (receive). the trx bit is cleared to ??in one of the following conditions. when arbitration lost is detected. when a stop condition is detected. when occurence of a start condition is disabled by the start condition duplication prevention function (note). with mst = ??and when a start condition is detected. with mst = ??and when ack non-return is detected. at reset m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 40 of 170 (8) bit 7: communication mode specification bit (master/slave specification bit: mst) this bit is used for master/slave specification for data communica- tion. when this bit is ?,?the slave is specified, so that a start condition and a stop condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. when this bit is ?,?the master is specified and a start condition and a stop condition are gener- ated, and also the clocks required for data communication are gen- erated on the scl. the mst bit is cleared to ??in one of the following conditions. immediately after completion of 1-byte data transmission when arbitration lost is detected when a stop condition is detected. when occurence of a start condition is disabled by the start condition duplication preventing function (note). at reset fig. 8.6.7 i 2 c status register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i 2 c status register (s1) [address 00f8 16 ] i 2 c s t a t u s r e g i s t e r 0 3 4 5 6, 7 b 7 b 6 0 0 : slave recieve mode 0 1 : slave transmit mode 1 0 : master recieve mode 1 1 : master transmit mode 1 2 0 0 0 1 0 b nam e function s a f t e r r e s e t r w c o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s ( t r x , m s t ) 0 : b us f ree 1 : bus busy b u s b u s y f l a g ( b b ) 0 : i nterrupt request i ssue d 1 : no interrupt request issued i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( p i n ) 0 : n ot d etecte d 1 : detected a r b i t r a t i o n l o s t d e t e c t i n g f l a g ( a l ) ( s e e n o t e ) 0 : add ress m i smatc h 1 : address match s l a v e a d d r e s s c o m p a r i s o n f l a g ( a a s ) ( s e e n o t e ) 0 : n o genera l ca ll d etecte d 1 : general call detected g e n e r a l c a l l d e t e c t i n g f l a g ( a d 0 ) ( s e e n o t e ) 0 : l ast bi t = 0 1 : last bit = 1 l a s t r e c e i v e b i t ( l r b ) ( s e e n o t e ) n o t e : t h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . i n d e t e r m i n a t e r r r r rw r w 0 r w ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) fig. 8.6.8 interrupt request signal generation timing sc l pin iicir q note: the start condition duplication prevention function disables the start condition generation, reset of bit counter reset, and scl output, when the following condition is satisfied: a start condition is set by another master device. rev.1.01 2003.07.16 page 41 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp 8.6.6 start condition generation method when the eso bit of the i 2 c control register (address 00f9 16 ) is ?, execute a write instruction to the i 2 c status register (address 00f8 16 ) to set the mst, trx and bb bits to ?.? a start condition will then be generated. after that, the bit counter becomes ?00 2 ?and an scl for 1 byte is output. the start condition generation timing and bb bit set timing are different in the standard clock mode and the high- speed clock mode. refer to figure 8.6.9 for the start condition generation timing diagram, and table 8.6.2 for the start condition/ stop condition generation timing table. fig. 8.6.9 start condition generation timing diagram i 2 c status register write signal set time for bb flag hold time setup time scl sda bb flag setup time 8.6.7 stop condition generation method when the eso bit of the i 2 c control register (address 00f9 16 ) is ?, execute a write instruction to the i 2 c status register (address 00f8 16 ) for setting the mst bit and the trx bit to ??and the bb bit to ?? a stop condition will then be generated. the stop condition genera- tion timing and the bb flag reset timing are different in the standard clock mode and the high-speed clock mode. refer to figure 8.6.10 for the stop condition generation timing diagram, and table 8.6.2 for the start condition/stop condition generation timing table. fig. 8.6.10 stop condition generation timing diagram table 8.6.2 start condition/stop condition generation tim- ing table item setup time hold time set/reset time for bb flag standard clock mode 4.25 s (17 cycles) 5.0 s (20 cycles) 3.0 s (12 cycles) high-speed clock mode 1.75 s (7 cycles) 2.5 s (10 cycles) 1.5 s (6 cycles) note: absolute time at = 4 mhz. the value in parentheses denotes the number of cycles. i 2 c status register write signal reset time for bb flag hold time setup time scl sda bb flag m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 42 of 170 8.6.8 start/stop condition detect conditions the start/stop condition detect conditions are shown in figure 8.6.11 and table 8.6.3. only when the 3 conditions of table 8.6.3 are satisfied, a start/stop condition can be detected. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal ?icirq?is generated to the cpu. fig. 8.6.11 start condition/stop condition detect timing dia- gram standard clock mode 6.5 s (26 cycles) < scl release time 3.25 s (13 cycles) < setup time 3.25 s (13 cycles) < hold time high-speed clock mode 1.0 s (4 cycles) < scl release time 0.5 s (2 cycles) < setup time 0.5 s (2 cycles) < hold time table 8.6.3 start condition/stop condition detect conditions note: absolute time at = 4 mhz. the value in parentheses denotes the num- ber of cycles. hold time setup time scl sda (start condition) sda (stop condition) scl release time hold time setup time 8.6.9 address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective ad- dress communication formats is described below. (1) 7-bit addressing format to meet the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00f9 16 ) to ?.?the first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the i 2 c address register (address 00f7 16 ). at the time of this comparison, address comparison of the rbw bit of the i 2 c address register (address 00f7 16 ) is not made. for the data transmission format when the 7-bit addressing format is selected, refer to figure 8.6.12, (1) and (2). (2) 10-bit addressing format to meet the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00f9 16 ) to ?.?an address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the i 2 c address register (address 00f7 16 ). at the time of this comparison, an address com- parison between the rbw bit of the i 2 c address register (address __ 00f7 16 ) and the r/w bit which is the last bit of the address data transmitted from the master is made. in the 10-bit addressing mode, __ the r/w bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. when the first-byte address data matches the slave address, the aas bit of the i 2 c status register (address 00f8 16 ) is set to ?.?after the second-byte address data is stored into the i 2 c data shift register (address 00f6 16 ), make an address comparison between the sec- ond-byte data and the slave address by software. when the address data of the 2nd bytes matches the slave address, set the rbw bit of the i 2 c address register (address 00f7 16 ) to ??by software. this processing can match the 7-bit slave address and r/w data, which are received after a restart condition is detected, with the value of the i 2 c address register (address 00f7 16 ). for the data transmis- sion format when the 10-bit addressing format is selected, refer to figure 8.6.12, (3) and (4). rev.1.01 2003.07.16 page 43 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp 8.6.10 example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz and in the ack return mode is shown below. ? set a slave address in the high-order 7 bits of the i 2 c address register (address 00f7 16 ) and ??in the rbw bit. ? set the ack return mode and scl = 100 khz by setting ?5 16 ?in the i 2 c clock control register (address 00fa 16 ). ? set ?0 16 ?in the i 2 c status register (address 00f8 16 ) and hold the scl at the high. ? set a communication enable status by setting ?8 16 ?in the i 2 c control register (address 00f9 16 ). ? set the address data of the destination of transmission in the high- order 7 bits of the i 2 c data shift register (address 00f6 16 ) and set ??in the least significant bit. ? set ?0 16 ?in the i 2 c status register (address 00f8 16 ) to generate a start condition. at this time, an scl for 1 byte and an ack clock automatically occurs. ? set transmit data in the i 2 c data shift register (address 00f6 16 ). at this time, an scl and an ack clock automatically occurs. ? when transmitting control data of more than 1 byte, repeat step ? . ? set ?0 16 ?in the i 2 c status register (address 00f8 16 ). after this, if ack is not returned or transmission ends, a stop condition will be generated. 8.6.11 example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, in the ack non-return mode, using the addressing format, is shown below. ? set a slave address in the high-order 7 bits of the i 2 c address register (address 00f7 16 ) and ??in the rbw bit. ? set the no ack clock mode and scl = 400 khz by setting ?5 16 ?in the i 2 c clock control register (address 00fa 16 ). ? set ?0 16 ?in the i 2 c status register (address 00f8 16 ) and hold the scl at the high. ? set a communication enable status by setting ?8 16 ?in the i 2 c control register (address 00f9 16 ). ? when a start condition is received, an address comparison is made. ? ?hen all transmitted address are??(general call): ad0 of the i 2 c status register (address 00f8 16 ) is set to ??nd an interrupt request signal occurs. ?hen the transmitted addresses match the address set in ? : ass of the i 2 c status register (address 00f8 16 ) is set to ??and an interrupt request signal occurs. ?n the cases other than the above: ad0 and aas of the i 2 c status register (address 00f8 16 ) are set to ??and no interrupt request signal occurs. ? set dummy data in the i 2 c data shift register (address 00f6 16 ). ? when receiving control data of more than 1 byte, repeat step ? . ? when a stop condition is detected, the communication ends. m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 44 of 170 fig. 8.6.12 address data communication format s slave address a data a data a/a p r/w 7 bits 0 1 to 8 bits 1 to 8 bit s s slave address a data a data a p 7 bits 1 1 to 8 bits 1 to 8 bit s (1) a master-transmitter transmits data to a slave-receiver s slave address 1st 7 bits a a data 7 bits 0 8 bits 1 to 8 bits (2) a master-receiver receives data from a slave-transmitte r slave address 2nd byte a data a/ a p 1 to 8 bits s slave address 1st 7 bits a a 7 bits 0 8 bits 7 bit s (3) a master-transmitter transmits data to a slave-receiver with a 10-bit address slave address 2nd byte data 1 to 8 bits sr slave address 1st 7 bits a data a p 1 to 8 bits 1 (4) a master-receiver receives data from a slave-transmitter with a 10-bit address s : start condition p : stop condition a : ack bit r/w : read/write bit sr : restart condition from master to slave from slave to master r/w r/w r/w r/w 8.6.12 precautions when using multi-master i 2 c-bus interface (1) read-modify-write instruction the precautions when the read-modify-write instruction such as seb, clb etc. is executed for each register of the multi-master i 2 c-bus interface are described below. ? 2 c data shift register (s0) when executing the read-modify-write instruction for this register during transfer, data may become a value not intended. ? 2 c address register (s0d) when the read-modify-write instruction is executed for this register at detecting the stop condition, data may become a value not ______ intended. it is because hardware changes the read/write bit (rbw) at the above timing. ? 2 c status register (s1) do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. ? 2 c control register (s1d) when the read-modify-write instruction is executed for this register at detecting the start condition or at completing the byte transfer, data may become a value not intended. because hardware changes the bit counter (bc0?c2) at the above timing. ? 2 c clock control register (s2) the read-modify-write instruction can be executed for this register. (2) start condition generating procedure using multi-master ? procedure example (the necessary conditions of the generating procedure are described as the following ? to ? ). lda (taking out of slave address value) sei (interrupt disabled) bbs 5,s1,busbusy (bb flag confirming and branch process) busfree: sta s0 (writing of slave address value) ldm #$f0, s1 (trigger of start condition generating) cli (interrupt enabled) busbusy: cli (interrupt enabled) ? use ?ta,? ?tx?or ?ty?of the zero page addressing instruction for writing the slave address value to the i 2 c data shift register. ? use ?dm?instruction for setting trigger of start condition gener- ating. ? write the slave address value of above ? and set trigger of start condition generating of above ? continuously shown the above procedure example. ? disable interrupts during the following three process steps: ?bb flag confirming ?writing of slave address value ?trigger of start condition generating when the condition of the bb flag is bus busy, enable interrupts immediately. rev.1.01 2003.07.16 page 45 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp (3) restart condition generating procedure ? procedure example (the necessary conditions of the generating procedure are described as the following ? to ? .) execute the following procedure when the pin bit is ?. ldm #$00, s1 (select slave receive mode) lda (taking out of slave address value) sei (interrupt disabled) sta s0 (writing of slave address value) ldm #$f0, s1 (trigger of restart condition generating) cli (interrupt enabled) ? select the slave receive mode when the pin bit is ?.?do not write ??to the pin bit. neither ??nor ??is specified for the writing to the bb bit. the trx bit becomes ??and the sda pin is released. ? the scl pin is released by writing the slave address value to the i 2 c data shift register. use ?ta,??tx?or ?ty?of the zero page addressing instruction for writing. ? use ?dm?instruction for setting trigger of restart condition gen- erating. ? write the slave address value of above ? and set trigger of re- start condition generating of above ? continuously shown the above procedure example. ? disable interrupts during the following two process steps: ?writing of slave address value ?trigger of restart condition generating (4) stop condition generating procedure ? procedure example (the necessary conditions of the generating procedure are described as the following ? to ? .) sei (interrupt disabled) ldm #$c0, s1 (select master transmit mode) nop (set nop) ldm #$d0, s1 (trigger of stop condition generating) cli (interrupt enabled) ? write ??to the pin bit when master transmit mode is select. ? execute ?op?instruction after setting of master transmit mode. also, set trigger of stop condition generating within 10 cycles af- ter selecting of master trasmit mode. ? disable interrupts during the following two process steps: ?select of master transmit mode ?trigger of stop condition generating (5) writing to i 2 c status register do not execute an instruction to set the pin bit to ??from ??and an instruction to set the mst and trx bits to ??from ??simultaneously. it is because it may enter the state that the scl pin is released and the sda pin is released after about one machine cycle. do not ex- ecute an instruction to set the mst and trx bits to ??from ??si- multaneously when the pin bit is ?.?it is because it may become the same as above. (6) process of after stop condition generat- ing do not write data in the i 2 c data shift register s0 and the i 2 c status register s1 until the bus busy flag bb becomes ??after generating the stop condition in the master mode. it is because the stop condition waveform might not be normally generated. reading to the above registers do not have the problem. m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 46 of 170 8.7 pwm output circuit this microcomputer is equipped with eight 8-bit pwms (pwm0 pwm7). pwm0?wm7 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 s and repeat pe- riod of 1024 s (for f(x in ) = 8 mhz) . figure 8.7.1 shows the pwm block diagram. the pwm timing gen- erating circuit applies individual control signals to pwm0?wm7 us- ing f(x in ) divided by 2 as a reference signal. 8.7.1 data setting when outputting pwm0?wm7, set 8-bit output data to the pwmi register (i means 0 to 7; addresses 0200 16 to 0207 16 ). 8.7.2 transmitting data from register to pwm circuit data transfer from the pwm register to the pwm circuit is executed at writing data to the register. the signal output from the pwm output pin corresponds to the con- tents of this register. 8.7.3 pwm operation the following explains pwm operation. first, set the bit 0 of pwm mode register 1 (address 020a 16 ) to ? (at reset, bit 0 is already set to ??automatically), so that the pwm count source is supplied. pwm0?wm3 are also used as pins p0 4 ?0 7 , pwm4?wm6 are also used as pins p0 0 ?0 2 , and pwm7 is also used as pin p0 3 re- spectively. set the corresponding bits of the port p0 direction reg- ister to ??(output mode). and select each output polarity by bit 3 of pwm mode register 1 (address 020a 16 ). then, set bits 7 to 0 of pwm mode register 2 to ??(pwm output). the pwm waveform is output from the pwm output pins by setting these registers. figure 8.7.2 shows the pwm timing. one cycle (t) is composed of 256 (2 8 ) segments. the 8 kinds of pulses, relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. refer to figure 8.7.2 (a). the pwm outputs waveform which is the logical sum (or) of pulses corresponding to the contents of bits 0 to 7 of the pwm register. several examples are shown in figure 8.7.2 (b). 256 kinds of output (high area: 0/256 to 255/256) are selected by changing the contents of the pwm register. a length of entirely high cannot be output, i.e. 256/256. 8.7.4 output after reset at reset, the output of port p0 is in the high-impedance state, and the contents of the pwm register and the pwm circuit are unde- fined. note that after reset, the pwm output is undefined until setting the pwm register. rev.1.01 2003.07.16 page 47 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp fig. 8.7.1 pwm block diagram pn pw p0 d0 : pwm mode register 1 [address 020a 16 ] : pwm mode register 2 [address 020b 16 ] : port p0 register [address 00c0 16 ] : port p0 direction register [address 00c1 16 ] selection gate: connected to black side at reset. is as same contents with the others. pwm1 register (address 0201 16 ) pwm2 register (address 0202 16 ) pwm3 register (address 0203 16 ) pwm4 register (address 0204 16 ) pwm5 register (address 0205 16 ) pwm6 register (address 0206 16 ) data bus pwm0 register (address 0200 16 ) b7 b0 8 pwm circuit pol p0 4 pw0 d0 4 pwm0 p0 5 pw1 d0 5 pwm1 p0 6 pw2 d0 6 pwm2 p0 7 pw3 d0 7 pwm3 p0 0 pw4 d0 0 pwm4 p0 1 pw5 d0 1 pwm5 p0 2 pw6 d0 2 pwm6 inside of pn0 1/ 2 x i n pwm timing generating circuit pwm7 register (address 0207 16 ) p0 3 pn4 d0 3 pwm7 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 48 of 170 fig. 8.7.2 pwm timing (a) pulses showing the weight of each bit 1 3 5 7 9 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255 4 12 20 28 36 44 52 60 68 76 84 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 8 16 48 80 112 144 176 208 240 24 40 56 72 88 104 120 136 152 168 184 200 216 232 248 32 96 160 224 64 192 bit 7 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 128 bit 0 pwm output t = 4 s t = 1024 s f(x in ) = 8 mhz (b) example of 8-bit pwm t 00 16 (0) 01 16 (1) 18 16 (24) ff 16 (255) t = 256 t rev.1.01 2003.07.16 page 49 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.7.3 pwm mode register 1 fig. 8.7.4 pwm mode register 2 b 7 b 6 b 5 b 4 b 3 b 2 b1 b 0 pwm mode register 1 (pn) [address 020a 16 ] b after reset r w pwm mode re g ister 1 0 1, 2 0 nam e function s nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. r r pwm counts source selection bit (pn0) 0 : count source supply 1 : count source stop 3 pwm output polarity selection bit (pn3) 0 0 : positive polarity 1 : negative polarity r w 4 p0 3 /pwm7 output selection bit (pn4) 0 0 : p0 3 output 1 : pwm7 output r w 0 w 5 to 7 nothing is assigned. these bits are write disable bits. wh e n t h ese b i ts a r e r ead out, t h e v a l ues a r e 0 . r 0 b7 b6 b5 b4 b3 b2 b1 b0 pwm mode register 2 (pw) [address 020b 16 ] b after reset rw pwm mode register 2 0 1 2 3 4 0 name functions p0 4 /pwm0 output selection bit (pw0) 0 : p0 4 output 1 : pwm0 output p0 6 /pwm2 output selection bit (pw2) 0 : p0 6 output 1 : pwm2 output p0 7 /pwm3 output selection bit (pw3) 0 : p0 7 output 1 : pwm3 output p0 0 /pwm4 output selection bit (pw4) 0 : p0 0 output 1 : pwm4 output 5 p0 1 /pwm5 output selection bit (pw5) 0: p0 1 output 1: pwm5 output 7 p0 5 /pwm1 output selection bit (pw1) 0 : p0 5 output 1 : pwm1 output 0 0 0 0 0 0 rw rw rw rw rw rw rw 6 p0 2 /pwm6 output selection bit (pw6) 0: p0 2 output 1: pwm6 output 0 rw fix this bit to 0. 0 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 50 of 170 8.8 a-d converter 8.8.1 a-d conversion register (ad) a-d conversion reigister is a read-only register that stores the result of an a-d conversion. this register should not be read during a-d conversion. 8.8.2 a-d control register (adcon) the a-d control register controls a-d conversion. bits 2 to 0 of this register select analog input pins. when these pins are not used as analog input pins, they are used as ordinary i/o pins. bit 3 is the a-d conversion completion bit, a-d conversion is started by writing 0 to this bit. the value of this bit remains at 0 during an a-d conversion, then changes to 1 when the a-d conversion is completed. bit 4 controls connection between the resistor ladder and v cc . when not using the a-d converter, the resistor ladder can be cut off from the internal v cc by setting this bit to 0, accordingly providing low- power dissipation. 8.8.3 comparison voltage generator (resistor ladder) the voltage generator divides the voltage between v ss and v cc by 256, and outputs the divided voltages to the comparator as the refer- ence voltage v ref . 8.8.4 channel selector the channel selector connects an analog input pin, selected by bits 2 to 0 of the a-d control register, to the comparator. 8.8.5 comparator and control circuit the conversion result of the analog input voltage and the reference voltage v ref is stored in the a-d conversion register. the a-d con- version completion bit and a-d conversion interrupt request bit are set to 1 at the completion of a-d conversion. fig. 8.8.1 a-d comparator block diagram a-d control register (address 00ef 16 ) a-d control circuit data bus switch tree a-d conversion interrupt request resistor ladder compa- rator channel selector a-d conversion register ad1 ad2 ad3 ad4 (address 00ee 16 ) b7 b0 3 8 v ss v cc ad5 ad6 ad7 ad8 rev.1.01 2003.07.16 page 51 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.8.2 a-d control register a-d control register b7 b6 b5 b4 b3 b2 b1 b0 a-d control register (adcon) [address 00ef 16 ] b after reset rw 0 to 2 analog input pin selection bits (adin0 to adin2) name functions b2 b1 b0 0 0 0 : ad1 0 0 1 : ad2 0 1 0 : ad3 0 1 1 : ad4 1 0 0 : ad5 1 0 1 : ad6 1 1 0 : ad7 1 1 1 : ad8 4 v cc connection selection bit (advref) 0: off 1: on 0 0 6 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is indeterminate. rw rw r 3 a-d conversion completion bit (adstr) 0: conversion in progress 1: convertion completed 1 rw 7 fix this bit to 0. rw 00 indeterminate 5 fix this bit to 0. rw 0 0 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 52 of 170 note: v ref indicates the reference voltage (= vcc). fig. 8.8.3 changes in a-d conversion register and comparison voltage during a-d conversion 8.8.6 conversion method ? set bit 7 of the interrupt input polarity register (address 0212 16 ) to 1 to generate an interrupt request at completion of a-d conver- sion. ? set the a-d conversion int3 interrupt request bit to 0 (even when a-d conversion is started, the a-d conversion int3 inter- rupt reguest bit is not set to 0 automatically). ? when using a-d conversion interrupt, enable interrupts by setting a-d conversion int3 interrupt request bit to 1 and setting the interrupt disable flag to 0. ? set the v cc connection selection bit to 1 to connect v cc to the resistor ladder. ? select analog input pins by the analog input selection bit of the a-d control register. ? set the a-d conversion completion bit to 0. this write operation starts the a-d conversion. do not read the a-d conversion register during the a-d conversion. ? verify the completion of the conversion by the state ( 1 ) of the a-d conversion completion bit, the state ( 1 ) of a-d conversion int3 interrupt reguest bit, or the occurrence of an a-d conversion interrupt. ? read the a-d conversion register to obtain the conversion results. note : when the ladder resistor is disconnect from v cc , set the v cc connec- tion selection bit to 0 between steps ? and ? . 8.8.7 internal operation when the a-d conversion starts, the following operations are auto- matically performed. ? the a-d conversion register is set to 00 16 . ? the most significant bit of the a-d conversion register becomes 1, and the comparison voltage v ref is input to the comparator. at this point, v ref is compared with the analog input voltage v in . ? bit 7 is determined by the comparison results as follows. when v ref < v in : bit 7 holds 1 when v ref > v in : bit 7 becomes 0 with the above operations, the analog value is converted into a digi- tal value. the a-d conversion terminates in a maximum of 50 ma- chine cycles (12.5 s at f(x in ) = 8 mhz) after it starts, and the con- version result is stored in the a-d conversion register. an a-d conversion interrupt request occurs at the same time as a-d conversion completion, the a-d conversion int3 interrupt request bit becomes 1. the a-d conversion completion bit also becomes 1. table 8.8.1 expression for v ref and v ref a-d conversion register contents n (decimal notation) 0 1 to 255 vref (v) 0 v ref 2 v ref 512 v ref 2 v ref 4 v ref 512 v ref 2 v ref 4 v ref 8 v ref 512 v ref 2 v ref 4 v ref 8 v ref 512 v ref 256 12 3 456 78 1 0000000 12 100000 1000000 1 123456 7 1 00000 000 contents of a-d conversion register reference voltage (v ref ) [v] 0 a-d conversion start 1st comparison start 3rd comparison start 8th comparison start 2nd comparison start digital value corresponding to analog input voltage. a-d conversion completion (8th comparison completion) ....... : value determined by mth (m = 1 to 8) result m ..... v ref 256 ? (n 0.5) rev.1.01 2003.07.16 page 53 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 8.8.8 definition of a-d conversion accuracy the definition of a-d conversion accuracy is described below (refer to figure 8.8.4). accuracy is shown the difference between measurement result out- put code and output code which is expected for a-d conversion whose specification is ideal by using lsb. the analog input voltage in accuracy measurement is made to be a middle point of input voltage width (=1 lsb) which outputs the code in which the a-d converter with the ideal characteristics is identical. for example, 1 lsb s width is 20 mv at v ref = 5.12v. 0 mv, 20 mv, 40 mv and 60 mv are selected for analog input voltage. a-d conversion accuracy is shown in fig 8.8.4. that the output code expected in the ideal a-d converter is 05 16 shows that there is actual a-d conversion result with in 03 16 to 07 16 on the = 2lsb absolute accuracy, when the analog input voltage is 100 mv. and, zero error and scale error are contained for the absolute accu- racy, and the quantization error is not contained. fig. 8.8.4 definition of a-d conversion accuracy output code 0 analog input voltage (mv) 20 40 80 100 120 140 160 180 200 220 00 16 01 16 02 16 03 16 04 16 05 16 06 16 07 16 08 16 09 16 + 2lsb 2lsb 60 absolute accuracy limitless resolution a-d conversion characteristics ideal a-d conversion characteristics m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 54 of 170 fig. 8.9.2 rom correction enable register fig. 8.9.1 rom correction address registers 8.9 rom correction function this can correct program data in rom. up to 2 addresses can be corrected, a program for correction is stored in the rom correction vector in ram as the top address. the rom correction vectors are 2 vectors. vector 1 : address 02c0 16 vector 2 : address 02e0 16 set the address of the rom data to be corrected into the rom cor- rection address register. when the value of the counter matches the rom data address in the rom correction vector as the top address, the main program branches to the correction program stored in the rom memory for correction. to return from the correction program to the main program, the op code and operand of the jmp instruction (total of 3 bytes) are necessary at the end of the correction program. the rom correction function is controlled by the rom correction enable register. notes 1: specify the first address (op code address) of each instruction as the rom correction address. 2: use the jmp instruction (total of 3 bytes) to return from the correction program to the main program. 3: do not set the same rom correction address to vectors 1 and 2. 4: for the m37281mkh-xxxsp and m37281eksp, when using the ex- pansion rom (bk7 = ??, the rom correction function do not oper- ate used for addresses 1000 16 to1fff 16 . note that on programming. 020c 16 rom correction address 1 (high-order) 020d 16 rom correction address 1 (low-order) 020e 16 rom correction address 2 (high-order) 020f 16 rom correction address 2 (low-order) b7 b6 b5 b4 b3 b2 b1 b0 rom correction enable register (rcr) [address 0210 16 ] b after reset rw rom correction enable register 0 vector 1 enable bit (rcr0) name functions 0: disabled 1: enabled 1 vector 2 enable bit (rcr1) 0: disabled 1: enabled 4 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 0 0 rw rw r 0 0 2, 3 fix these bits to 0. 0 rw rev.1.01 2003.07.16 page 55 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 8.10 data slicer this microcomputer includes the data slicer function for the closed caption decoder (referred to as the ccd). this function takes out the caption data superimposed in the vertical blanking interval of a com- posite video signal. a composite video signal which makes the sync chip s polarity negative is input to the cv in pin. when the data slicer function is not used, the data slicer circuit and the timing signal generating circuit can be cut off by setting bit 0 of the data slicer control register 1 (address 00e0 16 ) to 0. these set- tings can realize the low-power dissipation. fig. 8.10.1 data slicer block diagram composite video signal 1 m ? ? ? reference voltage generating circuit v hold 1000 pf high-order low-orde r data slicer on/off caption data register 4 (address 00e5 16 ) caption data register 3 (address 00e4 16 ) external circuit note : make the length of wiring which is connected to v hold , hlf, and cv in pin as short as possible so that a leakage current may not be generated when mounting a resistor or a capacitor on each pin. m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 56 of 170 8.10.1 notes when not using data slicer when bit 0 of data slicer control register 1 (address 00e0 16 ) is 0, terminate the pins as shown in figure 8.10.2. fig. 8.10.2 termination of data slicer input/output pins when data slicer circuit and timing generating circuit is in off state when both bits 0 and 2 of data slicer control register 1 (address 00e0 16 ) are 1, terminate the pins as shown in figure 8.10.3. fig. 8.10.3 termination of data slicer input/output pins when timing signal generating circuit is in on state rev.1.01 2003.07.16 page 57 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp figures 8.10.4 and 8.10.5 the data slicer control registers. fig. 8.10.4 data slicer control register 1 fig. 8.10.5 data slicer control register 2 b7 b6 b5 b4 b3 b2 b1 b0 data slicer control register 1(dsc1) [address 00e0 16 ] data slicer control register 1 00 rw 0rw 2 reference clock source selection bit (dsc12) 0: video signal 1: h sync signal 0r w 0rw 00 0: stopped 1: operating data slicer and timing signal generating circuit control bit (dsc10) fix these bits to 0. 3 to 7 000 10: f2 1: f1 selection bit of data slice reference voltage generating field (dsc11) definition of fields 1 (f1) and 2 (f2) h sep v sep f1: h sep v sep f2: b after reset r w name functions b7 b6 b5 b4 b3 b2 b1 b0 data slicer control register 2 (dsc2) [address 00e1 16 ] data slicer control register 2 0 indeterminate 0 indeterminate indeterminate 00 0: data is not latched yet and a clock-run-in is not determined. 1: data is latched and a clock-run-in is determined. caption data latch completion flag 1 (dsc20) fix this bit to 0. read-only test bit 30: f2 1: f1 field determination flag(dsc23) 4 0: method (1) 1: method (2) vertical synchronous signal (v sep ) generating method selection bit (dsc24) 0 5 0: match 1: mismatch v-pulse shape determination flag (dsc25) indeterminate b after reset function s nam e definition of fields 1 (f1) and 2 (f2) h sep v sep f1: h sep v sep f2: 0 indeterminate r w r r w r r r w r r w r fix this bit to 0. read-only test bit 6 7 1 2 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 58 of 170 8.10.2 clamping circuit and low-pass filter the clamp circuit clamps the sync chip part of the composite video signal input from the cv in pin. the low-pass filter attenuates the noise of clamped composite video signal. the cv in pin to which composite video signal is input requires a capacitor (0.1 ? 8.10.3 sync slice circuit this circuit takes out a composite sync signal from the output signal of the low-pass filter. 8.10.4 synchronous signal separation circuit this circuit separates a horizontal synchronous signal and a vertical synchronous signal from the composite sync signal taken out in the sync slice circuit. (1)horizontal synchronous signal (h sep ) a one-shot horizontal synchronizing signal hsep is generated at the falling edge of the composite sync signal. (2)vertical synchronous signal (v sep ) as a v sep signal generating method, it is possible to select one of the following 2 methods by using bit 4 of the data slicer control register 2 (address 00e1 16 ). method 1 the l level width of the composite sync signal is measured. if this width exceeds a certain time, a v sep signal is generated in synchronization with the rising of the timing signal immediately after this l level. method 2 the l level width of the composite sync signal is measured. if this width exceeds a certain time, it is detected whether a falling of the composite sync sig- nal exits or not in the l level period of the timing signal immediately after this l level. if a falling ex- ists, a v sep signal is generated in synchronization with the rising of the timing signal (refer to figure 8.10.6). figure 8.10.6 shows a v sep generating timing. the timing signal shown in the figure is generated from the reference clock which the timing generating circuit outputs. reading bit 5 of data slicer control register 2 permits determinating the shape of the v-pulse portion of the composite sync signal. as shown in figure 8.10.7, when the a level matches the b level, this bit is 0. in the case of a mismatch, the bit is 1. fig. 8.10.6 vsep generating timing (method 2) composite sync signal timing signal v sep signal measure l period a v sep signal is generated at a rising of the timing signal immediately after the l level width of the composite sync signal exceeds a certain time. rev.1.01 2003.07.16 page 59 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 8.10.5 timing signal generating circuit this circuit generates a reference clock which is 832 times as large as the horizontal synchronous signal frequency. it also generates various timing signals on the basis of the reference clock, horizontal synchronous signal and vertical synchronizing signal. the circuit operates by setting bit 0 of data slicer control register 1 (address 00e0 16 ) to 1. the reference clock can be used as a display clock for osd function in addition to the data slicer. the h sync signal can be used as a count source instead of the composite sync signal. however, when the h sync signal is selected, the data slicer cannot be used. a count source of the reference clock can be selected by bit 2 of data slicer control register 1 (address 00e0 16 ). for the pins hlf, connect a resistor and a capacitor as shown in figure 8.10.1. make the length of wiring which is connected to these pins as short as possible so that a leakage current may not be gener- ated. note: it takes a few tens of milliseconds until the reference clock becomes stable after the data slicer and the timing signal generating circuit are started. in this period, various timing signals, h sep signals and v sep sig- nals become unstable. for this reason, take stabilization time into con- sideration when programming. fig. 8.10.7 determination of v-pulse waveform composite sync signal a b 0 1 1 bit 5 of dsc2 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 60 of 170 8.10.6 data slice line specification circuit (1) specification of data slice line this circuit decides a line on which caption data is superimposed. the line 21 (fixed), 1 appropriate line for a period of 1 field (total 2 line for a period of 1 field), and both fields (f1 and f2) are sliced their data. the caption position register (address 00e6 16 ) is used for each setting (refer to table 8.10.1). the counter is reset at the falling edge of v sep and is incremented by 1 every h sep pulse. when the counter value matched the value specified by bits 4 to 0 of the caption position register, this h sep is sliced. the values of 00 16 to 1f 16 can be set in the caption position register (at setting only 1 appropriate line). figure 8.10.8 shows the signals in the vertical blanking interval. figure 8.10.9 shows the structure of the caption position register. (2) specification of line to set slice voltage the reference voltage for slicing (slice voltage) is generated for the clock run-in pulse in the particular line (refer to table 8.10.1). the field to generate slice voltage is specified by bit 1 of data slicer control register 1. the line to generate slice voltage 1 field is specified by bits 6, 7 of the caption position register (refer to table 8.10.1). fig. 8.10.8 signals in vertical blanking interval video signal vertical blanking interval composite video signal count value to be set in the caption position register ( 0f 16 in this case) h sep v sep h sep magnified drawing clock run-in start bit + 16-bit data start bit window for deteminating clock-run-in composite video signal line 21 1 appropriate line is set by the caption position register (when setting line 19) (3) field determination the field determination flag can be read out by bit 3 of data slicer control register 2. this flag charge at the falling edge of v sep . rev.1.01 2003.07.16 page 61 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.10.9 caption position register field and line to generate slice voltage field specified by bit 1 of dsc1 line 21 (total 1 line) field specified by bit 1 of dsc1 a line specified by bits 4 to 0 of cps (total 1 line) (see note 3) field specified by bit 1 of dsc1 line 21 (total 1 line) field specified by bit 1 of dsc1 line 21 and a line specified by bits 4 to 0 of cps (total 2 lines) (see note 2) field and line to be sliced data both fields of f1 and f2 line 21 and a line specified by bits 4 to 0 of cps (total 2 lines) (see note 2) both fields of f1 and f2 a line specified by bits 4 to 0 of cps (total 1 line) (see note 3) both fields of f1 and f2 line 21 (total 1 line) both fields of f1 and f2 line 21 and a line specified by bits 4 to 0 of cps (total 2 lines) (see note 2) cps b7 0 0 1 1 b6 0 1 0 1 notes 1: dsc1 is data slicer control register 1. cps is caption position register. 2: set 00 16 to 10 16 to bits 4 to 0 of cps. 3: set 00 16 to 1f 16 to bits 4 to 0 of cps. table 8.10.1 specification of data slice line b7 b6 b5 b4 b3 b2 b1 b0 caption position register (cps) [address 00e6 16 ] caption position registe r 0 to 4 0 r w 0 r w caption position bits(cps0 to cps4) 6, 7 refer to the corresponding table (table 8.10.1). slice line mode specification bits (in 1 field) (cps6, cps7) 5 0: data is not latched yet and a clock-run-in is not determined. 1: data is latched and a clock-run-in is determined. caption data latch completion flag 2 (cps5) indeterminate r b after reset functions nam e r w m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 62 of 170 8.10.7 reference voltage generating circuit and comparator the composite video signal clamped by the clamping circuit is input to the reference voltage generating circuit and the comparator. (1) reference voltage generating circuit this circuit generates a reference voltage (slice voltage) by us- ing the amplitude of the clock run-in pulse in line specified by the data slice line specification circuit. connect a capacitor between the v hold pin and the v ss pin, and make the length of wiring as short as possible so that a leakage current may not be gener- ated. (2) comparator the comparator compares the voltage of the composite video signal with the voltage (reference voltage) generated in the refer- ence voltage generating circuit, and converts the composite video signal into a digital value. fig. 8.10.10 clock run-in detect register 8.10.8 start bit detecting circuit this circuit detects a start bit at line decided in the data slice line specification circuit. the detection of a start bit is described below. ? ? ? 8.10.9 clock run-in determination circuit this circuit determinates clock run-in by counting the number of pulses in a window of the composite video signal. the reference clock count value in one pulse cycle is stored in bits 3 to 7 of the clock run-in detect register (address 00ea 16 ). read out these bits after the occurrence of a data slicer interrupt (refer to 8.10.12 interrupt request generating circuit ). figure 8.10.10 shows the structure of clock run-in detect register. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c l o c k r u n - i n d e t e c t r e g i s t e r ( c r d ) [ a d d r e s s 0 0 e a 1 6 ] r w c l o c k r u n - i n d e t e c t r e g i s t e r 0 to 2 0 r t e s t b i t s 3 to 7 n um b er o f re f erence c l oc k s to be counted in one clock run-in pulse period. c l o c k r u n - i n d e t e c t i o n b i t ( c r d 3 t o c r d 7 ) 0 r r e a d - o n l y b a f t e r r e s e t f u n c t i o n s n a m e rev.1.01 2003.07.16 page 63 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 8.10.10 data clock generating circuit this circuit generates a data clock synchronized with the start bit detected in the start bit detecting circuit. the data clock stores cap- tion data to the 16-bit shift register. when the 16-bit data has been stored and the clock run-in determination circuit determines clock run-in, the caption data latch completion flag is set. this flag is reset at a falling of the vertical synchronous signal (v sep ). fig. 8.10.11 data clock position register b7 b6 b5 b4 b3 b2 b1 b0 data clock position register (dps) [address 00eb 16 ] data clock position register 01 r w 3 data clock position set bits (dps3 to dps7) 1 r w fix these bits to 1. 1,2 fix this bit to 0. 0 r w 01 0 b function s name r w 4 to 7 0 after reset m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 64 of 170 8.10.11 16-bit shift register the caption data converted into a digital value by the comparator is stored into the 16-bit shift register in synchronization with the data clock. the contents of the high-order 8 bits of the stored caption data can be obtained by reading out data register 2 (address 00e3 16 ) and data register 4 (address 00e5 16 ). the contents of the low-order 8 bits can be obtained by reading out data register 1 (address 00e2 16 ) and data register 3 (address 00e4 16 ), respectively. these registers are reset to 0 at a falling of v sep . read out data registers 1 and 2 after the occurrence of a data slicer interrupt (refer to 8.10.12 inter- rupt request generating circuit ). 8.10.12 interrupt request generating circuit the interrupt requests as shown in table 8.10.3 are generated by combination of the following bits; bits 6 and 7 of the caption position register (address 00e6 16 ). read out the contents of data registers 1 to 4 and the contents of bits 3 to 7 of the clock run-in detect register after the occurrence of a data slicer interrupt request. slice line specification mode cps completion flag 1 (bit 0 of dsc2) completion flag 2 (bit 5 of cps) caption data registers 1, 2 caption data registers 3, 4 line 21 a line specified by bits 4 to 0 of cps line 21 line 21 a line specified by bits 4 to 0 of cps invalid invalid a line specified by bits 4 to 0 of cps 16-bit data of line 21 16-bit data of a line specified by bits 4 to 0 of cps 16-bit data of line 21 16-bit data of line 21 16-bit data of a line specified by bits 4 to 0 of cps invalid invalid 16-bit data of a line specified by bits 4 to 0 of cps contents of caption data latch completion flag contents of 16-bit shift register bit 7 0 0 1 1 bit 6 0 1 0 1 cps: caption position register dsc2: data slicer control register 2 table 8.10.2 contents of caption data latch completion flag and 16-bit shift register caption position register occurence souces of interrupt request at end of data slice line after slicing line 21 after a line specified by bits 4 to 0 of cps after slicing line 21 after slicing line 21 b7 0 1 b6 0 1 0 1 table 8.10.3 occurence sources of interrupt request rev.1.01 2003.07.16 page 65 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.10.12 sync pulse counter register 8.10.13 synchronous signal counter the synchronous signal counter counts the composite sync signal taken out from a video signal in the data slicer circuit or the vertical synchronous signal v sep as a count source. the count value in a certain time (t time) generated by f(x in )/2 13 or f(x in )/2 13 is stored into the 5-bit latch. accordingly, the latch value changes in the cycle of t time. when the count value exceeds 1f 16 , 1f 16 is stored into the latch. fig. 8.10.13 synchronous signal counter block diagram the latch value can be obtained by reading out the sync pulse counter register (address 00e9 16 ). a count source is selected by bit 5 of the sync pulse counter register. the synchronous signal counter is used when bit 0 of pwm mode register 1 (address 0208 16 ). figure 8.10.12 shows the structure of the sync pulse counter and figure 8.10.13 shows the synchronous signal counter block diagram. b7 b6 b5 b4 b3 b2 b1 b0 sync pulse counter register (hc) [address 00e9 16 ] r w sync pulse counter registe r 0 to 4 indeterminate r 6, 7 0 r count value (hc0 to hc4) 5 0 r w count source (hc5) 0: h sync signal 1: composite sync signal b after reset functions nam e nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. reset 5-bit counte r latch (5 bits) f(x in )/2 13 composite sync signal h sync signal counter sync pulse counter register data bus selection gate : connected to black side when reset. b5 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 66 of 170 8.11 osd functions table 8.11.1 outlines the osd functions. this osd function can display the following: the block display (32 characters ? 16 lines), the sprite display. and besides, the func- tion can display the both display at the same time. there are 3 dis- play modes and they are selected by a block unit. the display modes are selected by block control register i (i = 1 to 16). the features of each mode are described below. table.8.11.1 features of each display style 4 kinds ? 1, ? 2 1t c ? 1/2h, 1t c ? 1h smooth italic, under line, flash (blinking) 1 screen: 8 kinds (per character unit) max. 64 kinds possible (a character unit, 1 screen: 4 kinds, max. 64 kinds) layer 1 analog r, g, b output (each 4 adjustment levels : 64 colors), digital out1, out2 output font memory rom kinds of character sizes pre-divide ratio (note 1) dot size attribute character font coloring character background coloring display layer osd output (note 2) possible (a screen unit) raster coloring auto solid space function other function (note 3) triple layer osd function, window function, blank funtion possible display expansion (multiline display) 14 kinds ? 1, ? 2, ? 3 1t c ? 1/2h, 1t c ? 1h, 1.5t c ? 1/2h, 1.5t c ? 1h, 2t c ? 2h, 3t c ? 3h border possible (a character unit,1 screen: 16 kinds, max. 64 kinds) layer 1 and layer 2 layer 3 (with highest priority) 1 screen: 8 kinds (per dot unit) (only specified dots are colored per character unit ) max. 64 kinds 1 screen: 16 kinds (per character unit) max. 64 kinds 1 screen: 8 kinds (per dot unit) max. 64 kinds 8 kinds 1t c ? 1/2h, 1t c ? 1h, 2t c ? 1h, 2t c ? 2h ram ? 1, ? 2 notes1: the character size is specified with dot size and pre-divide ratio (refer to 8.11.3 dot size ). 2: sprite display do not output out2. 3: sprite display is not referred as windowed function. block display cc mode (closed caption mode) osd mode (on-screem display mode) cdosd mode (color dot on-screen display mode) sprite display display style parameter number of display 32 characters ? 16 lines 16 ? 20 dots (character display area: 16 ? 26 dots) dot structure kinds of characters 510 kinds 16 ? 26 dots 62 kinds 16 ? 20 dots 1 kind 1 character 16 ? 20 dots display position horizontal: 256 levels, vertical: 1024 levels horizontal: 2048 levels vertical: 1024 levels characters rev.1.01 2003.07.16 page 67 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp the osd circuit has an extended display mode. this mode allows multiple lines (16 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. figure 8.11.1 shows the configuration of osd character display area. figure 8.11.2 shows the block diagram of the osd circuit. figure 8.11.3 shows the osd control register 1. figure 8.11.4 shows the block control register i. fig. 8.11.1 configuration of osd character display area 1 6 d o t s 2 0 d o t s o s d m o d e u n d e r l i n e a r e a ? blank area ? b l a n k a r e a ? 16 dots 2 6 d o t s 2 0 d o t s ? : d i s p l a y e d o n l y i n c c m o d e . c c m o d e 16 2 6 d o t s cdosd mode m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 68 of 170 fig. 8.11.2 block diagram of osd circuit o s d r a m 1 8 b i t s ? 3 2 c h a r a c t e r s ? 1 6 l i n e s d a t a b u s o s d r o m ( c h a r a t e r f o n t ) 1 6 d o t s ? 2 0 d o t s ? 5 1 0 c h a r a c t e r s s h i f t r e g i s t e r s h i f t r e g i s t e r o u t p u t c i r c u i t r g b o u t 1 o u t 2 d i s p l a y o s c i l l a t i o n c i r c u i t o s c 1 o s c 2 h s y n c v s y n c d a t a s l i c e r c l o c k c l o c k f o r o s d o s d c o n t r o l c i r c u i t c o n t r o l r e g i s t e r f o r o s d o s d p o r t c o n t r o l r e g i s t e r o s d c o n t r o l r e g i s t e r 1 h o r i z o n t a l p o s i t i o n r e g i s t e r b l o c k c o n t r o l r e g i s t e r i o s d c o n t r o l r e g i s t e r 2 c l o c k c o n t r o l r e g i s t e r i / o p o l a r i t y c o n t r o l r e g i s t e r r a s t e r c o l o r r e g i s t e r o s d c o n t r o l r e g i s t e r 3 t o p b o r d e r c o n t r o l r e g i s t e r s 1 , 2 b o t t o m b o r d e r c o n t r o l r e g i s t e r s 1 , 2 v e r t i c a l p o s i t i o n r e g i s t e r s 1 i , 2 i c o l o r p a l l e t r e g i s t e r i l e f t b o r d e r c o n t r o l r e g i s t e r s 1 , 2 r i g h t b o r d e r c o n t r o l r e g i s t e r s 1 , 2 s p r i t e v e r t i c a l p o s i t i o n r e g i s t e r s 1 , 2 s p r i t e h o r i z o n t a l p o s i t i o n r e g i s t e r s 1 , 2 s p r i t e o s d c o n t r o l r e g i s t e r ( a d d r e s s 0 0 c b 1 6 ) ( a d d r e s s 0 0 c e 1 6 ) ( a d d r e s s 0 0 c f 1 6 ) ( a d d r e s s e s 0 0 d 0 1 6 t o 0 0 d f 1 6 ) ( a d d r e s s 0 2 1 5 1 6 ) ( a d d r e s s 0 2 1 6 1 6 ) ( a d d r e s s 0 2 1 7 1 6 ) ( a d d r e s s 0 2 1 8 1 6 ) ( a d d r e s s 0 2 1 9 1 6 ) ( a d d r e s s e s 0 2 1 c 1 6 , 0 2 1 e 1 6 ) ( a d d r e s s e s 0 2 1 d 1 6 , 0 2 1 f 1 6 ) ( a d d r e s s e s 0 2 2 0 1 6 t o 0 2 3 f 1 6 ) ( a d d r e s s e s 0 2 4 1 1 6 t o 0 2 4 7 1 6 , 0 2 4 9 1 6 t o 0 2 4 f 1 6 ) ( a d d r e s s e s 0 2 5 0 1 6 , 0 2 5 1 1 6 ) ( a d d r e s s e s 0 2 5 2 1 6 , 0 2 5 3 1 6 ) ( a d d r e s s e s 0 2 5 4 1 6 , 0 2 5 5 1 6 ) ( a d d r e s s e s 0 2 5 6 1 6 , 0 2 5 7 1 6 ) ( a d d r e s s e s 0 2 5 8 1 6 ) s h i f t r e g i s t e r o s d r o m ( c o l o r d o t f o n t ) 1 6 d o t s ? 2 6 d o t s ? 3 p l a n e s ? 6 2 c h a r a c t e r s r a m f o r o s d ( s p r i t e ) 1 6 d o t s ? 2 0 d o t s ? 3 p l a n e s s h i f t r e g i s t e r rev.1.01 2003.07.16 page 69 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.11.3 osd control register 1 0 : color signal of character background part does not flash 1 : color signal of character background part flashes b7 b6 b5 b4 b3 b2 b1 b0 osd control register 1 (oc1) [address 00ce 16 ] b name functions after reset r w osd control register 1 0 osd control bit (oc10) (see note 1) 0 : all-blocks display off 1 : all-blocks display on 0 1 scan mode selection bit ( oc11 ) 0 : normal scan mode 1 : bi-scan mode 0 2 0 : all bordered 1 : shadow bordered (see note 2) 0 0 4 automatic solid space control bit (oc14) 0 border type selection bit ( oc12 ) rw rw rw r w rw 3 flash mode selection bit ( oc13 ) 6, 7 0 0: logic sum (or) of layer 1 s color and layer 2 s color 0 1: layer 1 s color has priority 1 0: layer 2 s color has priority 1 1: do not set. layer mixing control bits (oc16, oc17) ( see note 3 ) b7 b6 0 : off 1 : on 0rw 5 vertical window/blank control bit (oc15) 0rw 0 : off 1 : on notes 1 : even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next v sync . 2: shadow border is output at right and bottom side of the font. 3: out2 is always ored, regardless of values of these bits. m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 70 of 170 b 7 b 6 b 5 b 4 b 3 b 2 b 1b 0 b l o c k c o n t r o l r e g i s t e r i ( b c i ) ( i = 1 t o 1 6 ) [ a d d r e s s e s 0 0 d 0 1 6 t o 0 0 d f 1 6 ] b l o c k c o n t r o l r e g i s t e r i 0 , 1 display mode selection bits (bci0, bci1) i n d e t e r m i n a t e 3 , 4 d o t s i z e s e l e c t i o n b i t s ( b c i 3 , b c i 4 ) 5, 6 pre-divide ratio selection bit (bci5, bci6) 7 b1 b0 0 0: display off 0 1: osd mode 1 0: cc mode 1 1: cdosd mode b n a m e function s a f t e r r e s e tr w r w i n d e t e r m i n a t e r w i n d e t e r m i n a t e r w i n d e t e r m i n a t e r notes 1: tc is osd clock cycle divided in pre-divide circuit. 2: h is h sync. 3: this character size is available only in layer 2. at this time, set layer 1 s pre-divide ratio = ? 2, layer 1 s horizontal dot size = 1tc. b 6 b 5 b 4 b 3 p r e - d i v i d e d o t s i z e r a t i o 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 1 1 ? 1 ? 2 ? 3 1tc ? 1/2h 1tc ? 1h 2tc ? 2h 3tc ? 3h 1tc ? 1/2h 1tc ? 1h 2tc ? 2h 3tc ? 3h 1.5tc ? 1/2h (see note 3) 1.5tc ? 1h (see note 3) 1tc ? 1/2h 1tc ? 1h 2tc ? 2h 3tc ? 3h 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is indeterminate. 2b o r d e r c o n t r o l b i t ( b c i 2 ) 0 : b o r d e r o f f 1 : b o r d e r o n i n d e t e r m i n a t e r w fig. 8.11.4 block control register i (i = 1 to 16) rev.1.01 2003.07.16 page 71 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 8.11.1 triple layer osd three built-in layers of display screens accommodate triple display of channels, volume, etc., closed caption, and sprite displays within layers 1 to 3. the layer to be displayed in each block is selected by bit 0 or 1 of the osd control register 2 for each display mode (refer to figure 8.11.7). layer 3 always displays the sprite display. table 8.11.2 mixing layer 1 and layer 2 block in layer 1 cc, osd, cdosd mode ? 1, ? 2 (cc mode) ? 1 to ? 3 (osd, cdosd mode) 1t c ? 1/2h, 1t c ? 1h (cc mode) 1t c ? 1h, 1t c ? 1/2h, 2t c ? 2h, 3t c ? 3h (osd, cdosd mode) arbitrary block parameter display mode pre-divide ratio dot size horizontal display start position vertical display start position when the layer 1 block and the layer 2 block overlay, the screen is composed (refer to figure 8.11.5) with layer mixing by bit 6 or 7 of the osd control register 1, as shown in figure 8.11.3. layer 3 al- ways takes display priority of layers 1 and 2. notes 1: when mixing layer 1 and layer 2, note table 8.11.2. 2: out2 is always ored, regardless of values of bits 6, 7 of the osd control register 1. and besides, even when out2 (layer 1 or layer 2) overlaps with sprite display (layer 3), out2 is output. block in layer 2 osd, cdosd mode same as layer 1 same size as layer 1 1.5t c can be selected only when: layer 1 s pre-divide ratio = ? 2 and layer 1 s horizontal dot size = 1t c . as this time, vertical dot size is the same as layer 1. same position as layer 1 pre-divide ratio = ? 2 1t c ? 1/2h, 1.5t c ? 1/2h 1t c ? 1h, 1.5t c ? 1h pre-divide ratio = ? 1 1t c ? 1/2h 1t c ? 1h arbitrary however, when dot size is 2t c ? 2h or 2t c ? 3h, set difference between vertical display position of layer 1 and that of layer 2 as follows. 2t c ? 2h: 2h units 3t c ? 3h: 3h units m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 72 of 170 fig. 8.11.6 display example of triple layer osd d i s p l a y e x a m p l e o f l a y e r 1 = h e l l o , l a y e r 2 = c h 5 ch 5 h e l l o l o g i c a l s u m ( o r ) o f l a y e r 1 s c o l o r a n d l a y e r 2 s c o l o r ( s e e n o t e ) b i t 7 = 0 , b i t 6 = 0 l a y e r 1 s c o l o r h a s p r i o r i t y b i t 7 = 0 , b i t 6 = 1 c h 5 h e l l o l a y e r 2 s c o l o r h a s p r i o r i t y b i t 7 = 1 , b i t 6 = 0 h e l l o c h 5 n o t e : l a y e r m i x i n g i s n o t l o g i c a l s u m ( o r ) o f c o l o r s , b u t t h a t o f e a c h b i t o f c o l o r p a l l e t r e g i s t e r . e x a m p l e ) w h e n l o g i c a l s u m ( o r ) i s p e r f o r m e d o n c o l o r p a l l e t 1 ( 0 0 0 1 2 ) a n d c o l o r p a l l e t 2 ( 0 0 1 0 2 ) , t h e c o l o r s e t t o c o l o r p a l l e t 3 ( 0 0 1 1 2 ) i s o u t p u t , r e g a r d l e s s o f c o l o r p a l l e t s 1 a n d 2 c o n t e n t s . fig. 8.11.5 triple layer osd l a y e r 2 l a y e r 1 b l o c k 1 b l o c k 2 b l o c k 7 b l o c k 8 . . . l a y e r 3 block 9 b l o c k 1 5 b l o c k 1 0 b l o c k 1 6 . . . s p r i t e r, g, b of layer 1 o u t 2 o f l a y e r 1 s p r i t e layer 1 sprite (except transparent) n o t e : w h e n l a y e r 1 a n d s p r i t e d i s p l a y o v e r l a y e a c h o t h e r , o n l y o u t 2 i n l a y e r 1 i s o u t p u t . a ' a rev.1.01 2003.07.16 page 73 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.11.7 osd control register 2 b7 b6 b5 b4 b3 b2 b1 b0 osd control register 2 (oc2) [address 0215 16 ] b name functions osd control register 2 0, 1 2 r, g, b signal output selection bit(oc22) 3 5 window/blank selection bit 1 (horizontal) (oc25) solid space output bit (oc23) 0: out1 output 1: out2 output 0: digital output 1: analog output (4 gradations) 4 horizotal window/blank coutrol bit (oc24) 0: off 1: on b1 b0 layer 1 layer 2 0 0 cc, osd, cdosd 0 1 cc, osd cdosd 1 0 cc, cdosd osd 1 1 cc cdosd osd 0: horizontal blank function 1: horizontal window function 6 window/blank selection bit 2 (vertical) (oc26) 0: vertical blank function 1: vertical window function 7 osd interrupt request selection bit (oc27) r w 0 r w 0 r w 0 r w 0 r w 0 r w 0 r w 0 r w 0: at completion of layer 1 block display 1: at completion of layer 2 block display display layer selection bits (oc20, oc21) note: when setting bit 1 of the osd port control register to 1, the value which is converted from the 4-adjustment-level analog to the 2-bit digital is output regardless of this bit value as follows : the high-order bit (r1, g1 and b1) is output from pins p5 2 , p5 3 and p5 4 , and the low-order bit is (r0, g0 and b0) output from pins p1 7 , p1 5 and p1 6 . and besides, when not using osd function, the low-power dissipation can realize by setting this bit to 0. (see note) after reset m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 74 of 170 8.11.2 display position the display start positions of characters are specified by a block. there are 16 blocks, blocks 1 to 16. up to 32 characters can be displayed in each block (refer to 8.11.6 memory for osd ). the display position of each block can be set in both horizontal and vertical directions by software. the display start position in the horizontal direction can be selected for all blocks in common from 256-step display positions in units of 4 t osc (t osc = osd oscillation cycle). the display start position in the vertical direction for each block can be selected from 1024-step display positions in units of 1 t h ( t h = h sync cycle). blocks are displayed in conformance with the following rules: when the display start position is overlapped with another block (figure 8.11.8 (b)), a lower block number (1 to 16) is displayed on the front. when another block display position appears while one block is displayed (figure 8.11.8 (c)), the block with a larger set value as the vertical display start position is displayed. however, do not dis- play block with the dot size of 2t c ? 2h or 3t c ? 3h during display period ( ? ) of another block. fig. 8.11.8 display position ? in the case of osd mode block: 20 dots in vertical from the vertical display start position. ? in the case of cc or cdosd mode block: 26 dots in vertical from the vertical display start position. hp vp12, vp22 block 1 block 2 (a) example when each block is separated vp13, vp23 block 3 hp vp11, vp21 = vp12, vp22 block 1 (b) example when block 2 overlaps with block 1 (block 2 is not displayed) hp vp11, vp21 vp12, vp22 (c) example when block 2 overlaps in process of block 1 block 1 block 2 note: vp1i or vp2i (i : 1 to 16) indicates the vertical display start position of display block i. vp11, vp21 rev.1.01 2003.07.16 page 75 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp the display start position in the vertical direction is determined by counting the horizontal sync signal (h sync ). at this time, when v sync and h sync are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of h sync signal from after fixed cycle of rising edge (falling edge) of v sync signal. so interval from rising edge (falling edge) of v sync signal to rising edge (falling edge) of h sync signal needs enough time (2 machine cycles or more) for avoiding jitter. the polarity of h sync and v sync signals can select with the i/o polarity control register (address 0217 16 ). fig. 8.11.9 supplement explanation for display position when bits 0 and 1 of the i/o polarity control register (address 0217 16 ) are set to 1 (negative polarity) v sync signal input v sync control signal in microcomputer 0.25 to 0.50 [ s] ( at f ( x in ) = 8mhz ) (note 2) not count 12345 notes 1 : the vertical position is determined by counting falling edge of h sync signal after rising edge of v sync control signal in the microcomputer. 2: do not generate falling edge of h sync signal near rising edge of v sync control signal in microcomputer to avoid jitter. 3: the pulse width of v sync and h sync needs 8 machine cycles or more. 8 machine c y cles or more 8 machine cycles or more h sync signal input period of counting h sync signal m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 76 of 170 fig. 8.11.10 vertical position register 1i (i = 1 to 16) the vertical start position for each block can be set in 1024 steps (where each step is 1t h (t h : h sync cycle)) as values 00 16 to ff 16 in vertical position register 1i (i = 1 to 16) (addresses 0220 16 to 022f 16 ) and values 00 16 to 03 16 in vertical position register 2i (i = 1 to 16) (addresses 0230 16 to 023f 16 ). the vertical position registers are shown in figures 8.11.10 and 8.11.11. fig. 8.11.11 vertical position register 2i (i = 1 to 16) b7 b6 b5 b4 b3 b2 b1 b0 vertical position register 1i (vp1i) (i = 1 to 16) [addresses 0220 16 to 022f 16 ] b name functions after reset rw vertical position register 1i 0 to 7 control bits of vertical display start positions (vp1i0 to vp1i7) (see note 1) vertical display start positions (low-order 8 bits) th ? (setting value of low-order 2 bits of vp2i ? 16 2 + setting value of low-order 4 bits of vp1i ? 16 1 + setting value of low-order 4 bits of vp1i ? 16 0 ) rw notes 1: do not 00 16 and 01 16 to vp1i at vp2i = 00 16 . 2: t h is cycle of h sync . 3: vp2i is vertical position register 2i. indeterminate b7 b6 b5 b4 b3 b2 b1 b0 vertical position register 2i (vp2i) (i = 1 to 16) [addresses 0230 16 to 023f 16 ] b name functions after reset r w vertical position register 2i 0, 1 control bits of vertical display start positions (vp2i0, vp2i1) (see note 1) vertical display start positions (high-order 2 bits) th ? (setting value of low-order 2 bits of vp2i ? 16 2 + setting value of low-order 4 bits of vp1i ? 16 1 + setting value of low-order 4 bits of vp1i ? 16 0 ) rw nothing ic assigned. these bits are write disable bits. when these bits are read out, the values are indeterminate. 2 to 7 r notes 1: do not set 00 16 and 01 16 to vp1i at vp2i = 00 16 . 2: t h is cycle of h sync . 3: vp1i is vertical position register 1i. indeterminate indeterminate rev.1.01 2003.07.16 page 77 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp note : 1t c (t c : osd clock cycle divided in pre-divide circuit) gap occurs be- tween the horizontal display start position set by the horizontal position register and the most left dot of the 1st block. accordingly, when 2 blocks have different pre-divide ratios, their horizontal display start position will not match. ordinaly, this gap is 1t c regardless of character sizes, however, the gap is 1.5t c only when the character size is 1.5t c . fig. 8.11.12 notes on horizontal display start position h sync 1t c 1t c block 1 (pre-divide ratio = 1) 1t c 4t osc ? n note 1 block 2 (pre-divide ratio = 2) block 3 (pre-divide ratio = 3) block 4 (pre-divide ratio = 2, character size = 1.5tc) 1.5t c : value of horizontal position register (decimal notation) : osd clock cycle divided in pre-divide circuit : osd oscillation cycle : 50 tosc n tc tosc tdef t def the horizontal display position is common to all blocks, and can be set in 256 steps (where 1 step is 4t osc , t osc being the oscillating cycle for display) as values 00 16 to ff 16 in bits 0 to 7 of the hori- zontal position register (address 00cf 16 ). the horizontal position reg- ister is shown in figure 8.11.12. fig. 8.11.11 horizontal position register b7 b6 b5 b4 b3 b2 b1 b0 horizontal position register (hp) [address 00cf 16 ] b name functions after reset rw horizontal position register control bits of horizontal display start positions (hp0 to hp7) horizontal display start positions 4t osc ? (setting value of high-order 4 bits ? 16 1 +setting value of low-order 4 bits ? 16 0 ) 0rw 0 to 7 notes 1. the setting value synchronizes with the v sync . 2. t osc = osd oscillation period. m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 78 of 170 8.11.3 dot size the dot size can be selected by a block unit. the dot size in vertical direction is determined by dividing h sync in the vertical dot size con- trol circuit. the dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the osd clock source (data slicer clock, osc1, main clock) in the pre-divide circuit. the clock cycle divided in the pre-divide circuit is defined as 1t c . the dot size is specified by bits 6 to 3 of the block control register. fig. 8.11.14 block diagram of dot size control circuit fig. 8.11.15 definition of dot sizes h sync synchronous cycle ? ? note: to use data slicer clock, set bit 0 of data slicer control register 1 to 1. data slicer clock (see note) 1 dot scanning line of f1 (f2) scanning line of f2 (f1) 1/2h 1h 2h 3h 3t c 2t c 1t c 1t c in normal scan mode refer to figure 8.11.4 (the block control register i), refer to figure 8.11.6 (the clock control register). the block diagram of dot size control circuit is shown in figure 8.11.14. notes 1: the pre-divide ratio = 3 cannot be used in the cc mode. 2: the pre-divide ratio of the layer 2 must be same as that of the layer 1 by the block control register i. 3: in the bi-scan mode, the dot size in the vertical direction is 2 times as ompared with the normal mode. refer to 8.11.13 scan mode about the scan mode. rev.1.01 2003.07.16 page 79 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp bit 7 of port p3 direction register clock control register 8.11.4 clock for osd as a clock for display to be used for osd, it is possible to select one of the following 3 types. data slicer clock output from the data slicer (approximately 26 mhz) clock from the lc oscillator supplied from the pins osc1 and osc2 clock from the ceramic resonator or the quartz-crystal oscillator from the pins osc1 and osc2 the clock for display to be used for osd can be selected by bit 7 of port p3 direction register, bit 2 and bit 1 of clock source control reg- ister (address 0216 16 ). if the pins osc1 and osc2 are not used as osd clock input/output, these pins can be used as the sub-clock input/output, or port p6. fig. 8.11.16 clock control register table 8.11.3 setting of p6 3 /osc1/x cin , p6 4 /osc2/x cout bit 2 bit 1 clock input/ output pins for osd sub-clock input/ output pins 0 0 0 function registers input port 1 0 1 0 1 0 1 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c l o c k c o n t r o l r e g i s t e r ( c s ) [ a d d r e s s 0 2 1 6 1 6 ] b n ame f u n c t i o n s a f t e r r e s e t r w c l o c k c o n t r o l r e g i s t e r 0 c l o c k s e l e c t i o n b i t ( c s 0 ) 0 r w 1, 2 0 : d a t a s l i c e r c l o c k 1 : o s c 1 c l o c k 0 r w 70 r w t est bi t (see note 2) osc 1 osc ill at i ng mo d e selection bits (cs1, cs2) 00 : 3 2 k h z o s c i l l a t i n g m o d e . 01 : u s e d a s i n p u t p o r t o f p 6 3 a n d p 6 4 ( s e e n o t e 1 ) . 10 : l c o s c i l l a t i n g m o d e 11 : c e r a m i c q u a r t z - c r y s t a l o s c i l l a t i n g m o d e b2 b1 n o t e 1 : s e t b i t 7 o f a d d r e s s 0 0 c 7 1 6 t o 1 , w h e n o s c 1 a n d o s c 2 a r e u s e d a s p 6 3 a n d p 6 4 . 2 : b e s u r e t o s e t b i t 7 t o 0 f o r p r o g r a m o f t h e m a s k a n d t h e e p r o m v e r s i o n s . f o r t h e e m u l a t o r m c u v e r s i o n ( m 3 7 2 8 0 e r s s ) , b e s u r e t o s e t b i t 7 t o 1 w h e n u s i n g t h e d a t a s l i c e r c l o c k f o r s o f t w a r e d e b u g g i n g . 00 0 f i x t h e s e b i t s t o 0 . 0 r w 3 to 6 0 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 80 of 170 fig. 8.11.17 block diagram of osd selection circuit 0 11 10 data slicer circuit data slicer clock osc1 clock lc c eram i c quartz-crysta l o sc ill at i ng mo d e f or osd cs2 , cs1 osd control circuit cs0 (see note) note : to use data slicer clock, set bit 0 of data slicer control register 1 to 1. 1 32khz 00 rev.1.01 2003.07.16 page 81 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 8.11.5 field determination display to display the block with vertical dot size of 1/2h, whether an even field or an odd field is determined through differences in a synchro- nizing signal waveform of interlacing system. the dot line 0 or 1 (re- fer to figure 8.11.19) corresponding to the field is displayed alter- nately. in the following, the field determination standard for the case where both the horizontal sync signal and the vertical sync signal are nega- tive-polarity inputs will be explained. a field determination is deter- mined by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the v sync control signal (refer to figure fig. 8.11.18 i/o polarity control register 8.11.9) in the microcomputer and then comparing this time with the time of the previous field. when the time is longer than the compar- ing time, it is regarded as even field. when the time is shorter, it is regarded as odd field. the field determination flag changes at a rising edge of v sync con- trol signal in the microcomputer. the contents of this field can be read out by the field determination flag (bit 7 of the i/o polarity control register at address 0217 16 ). a dot line is specified by bit 6 of the i/o polarity control register (refer to figure 8.11.19). however, the field determination flag read out from the cpu is fixed to 0 at even field or 1 at odd field, regardless of bit 6. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i / o p o l a r i t y c o n t r o l r e g i s t e r ( p c ) [ a d d r e s s 0 2 1 7 1 6 ] b n a m e f unct i on s a f t e r r e s e t r w i / o p o l a r i t y c o n t r o l r e g i s t e r 0 h sync i nput po l ar i ty switch bit (pc0) 0 : p os i t i ve po l ar i ty i nput 1 : negative polarity input 0 10 : p os i t i ve po l ar i ty i nput 1 : negative polarity input 0 2 r , g , b output po l ar i ty switch bit (pc2) 0 : p os i t i ve po l ar i ty output 1 : negative polarity output 0 3 0 v s y n c i n p u t p o l a r i t y s w i t c h b i t ( p c 1 ) r w r w r w r n ote: r e f er to fi g. 8.11.19. 0 : at even fi e ld at odd field 1 : at even field at odd field 4 o u t 1 o u t p u t p o l a r i t y s w i t c h b i t ( p c 4 ) 0 : p os i t i ve po l ar i ty output 1 : negative polarity output 0 5 o u t 2 o u t p u t p o l a r i t y s w i t c h b i t ( p c 5 ) 0 : p os i t i ve po l ar i ty output 1 : negative polarity output 0 6 d i s p l a y d o t l i n e s e l e c t i o n b i t ( p c 6 ) ( s e e n o t e ) 0 7 fi e ld d eterm i nat i on flag(pc7) 0 : e ven fi e ld 1 : odd field 1 r w r w r w r n ot hi ng i s ass i gne d . thi s bi t i s a wr i te di sa bl e bi t. when this bit is read out, the value is 0 . m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 82 of 170 fig. 8.11.19 relation between field determination flag and display font both h sync signal and v sync signal are negative-polarity input field even odd field determination flag(note) display dot line selection bit display dot line 0 (t2 > t1) 1 (t3 < t2) 0 1 0 1 when using the field determination flag, be sure to set bit 0 of the pwm mode register 1 (address 020a 16 ) to 0. t2 t3 osd rom font configuration diagram dot line 0 dot line 1 odd dot line 0 dot line 1 (n 1) field (odd-numbered) t1 0.25 to 0.50[ cdosd mode 1 35 79111315 1 3 5 7 9 11 13 15 17 19 21 23 25 26 24 22 20 18 16 14 12 10 8 6 4 2 24 6810121416 1 3 5 7 9 11 13 15 17 19 20 18 16 14 12 10 8 6 4 2 13579111315 2 4 6 8 10 12 14 16 osds mode h sync v sync and v sync control signal in microcom- puter upper : v sync signal lower : v sync control signal in micro- computer (n) field (even-numbered) (n+1) field (odd-numbered) when the display dot line selection bit is 0, the font is displayed at even field, the font is displayed at odd field. bit 7 of the i/o polarity control register can be read as the field determination flag : 1 is read at odd field, 0 is read at even field. note : the field determination flag changes at a rising edge of the v sync control signal (negative-polarity input) in the microcomputer. rev.1.01 2003.07.16 page 83 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 8.11.6 memory for osd there are 2 types of memory for osd : osd rom (addresses 10800 16 to 157ff 16 and 18000 16 to 1acff 16 ) used to specify char- acter dot data and osd ram (addresses 0700 16 to 07a7 16 and 0800 16 to 0fdf 16 ) used to specify the kinds of display characters, display colors, and sprite display. the following describes each type of memory. fig. 8.11.20 character font data storing address (1) osd rom (addresses 10800 16 to 157ff 16 , 18000 16 to 1acff 16 ) the dot pattern data for osd characters is stored in the charac- ter font area in the osd rom and the cd font data for osd characters is stored in the color dot font area in the osd rom. to specify the kinds of the character font and the cd font, it is necessary to write the character code into the osd ram. the modes are selected by bit 3 of the osd control register 3 for each screen. the character font data storing address is shown in figure 8.11.20. the cd font data storing address is shown in figure 8.11.21. the 510 kinds of character font and 62 kinds of cd font can be stored. character font line number 02 16 09 16 03 16 04 16 05 16 06 16 07 16 08 16 11 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 15 16 12 16 13 16 14 16 left area right area b 0 b7 b 0 b7 0a 16 osd rom address of character font data ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 osd rom address bit 1 line number area bit line number / character code / area bit character code 0 line number = 02 16 to 15 16 character code = 00 16 to 1ff 16 ( 0ff 16 and 100 16 can not be used. write ff 16 to corresponding addresses.) area bit = 0: left area 1: right area m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 84 of 170 fig. 8.11.21 color dot font data storing address 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 o s d r o m a d d r e s s o f c d f o n t d a t a a d 1 6 a d 1 5 a d 1 4 a d 1 3 a d 1 2 a d 1 1 a d 1 0 a d 9 a d 8 a d 7 a d 6 a d 5 a d 4 a d 3 a d 2 a d 1 a d 0 o s d r o m a d d r e s s b i t l i n e n u m b e r / c d c o d e / a r e a b i t 11 l i n e n u m b e r ( m s b t o l s b ) c d c o d e ( c 5 t o c 0 ) a r e a b i t p l a i n s e l e c t i o n b i t 1 d i s p l a y e x a m p l e li ne number 0 2 1 6 09 16 0 3 1 6 0 4 1 6 05 16 0 6 1 6 0 7 1 6 0 8 1 6 0 a 16 1 1 1 6 0 b 1 6 0 c 1 6 0 d 16 0 e 16 0 f 1 6 10 16 1 5 1 6 1 2 1 6 13 16 1 4 1 6 a r e a 0a r e a 1 b 0 b 7b 0 b 7 19 16 1 6 1 6 1 7 1 6 1 8 1 6 0 0 1 6 0 1 1 6 line number cd code area bit = 0 0 1 6 t o 1 9 1 6 = 0 0 1 6 t o 3 f 1 6 ( 1 f 1 6 a n d 2 0 1 6 c a n n o t b e u s e d . w r i t e f f 1 6 t o t h e c o r r e s p o n d i n g a d d r e s s . ) = 0 : a r e a 0 1 : a r e a 1 0 2 1 6 0 9 1 6 03 16 0 4 1 6 0 5 1 6 0 6 1 6 0 7 1 6 08 16 0 a 1 6 11 16 0 b 1 6 0 c 16 0 d 1 6 0 e 1 6 0 f 16 1 0 1 6 1 5 1 6 1 2 1 6 1 3 1 6 14 16 b 0 b 7b 0 b 7 1 9 1 6 1 6 1 6 1 7 1 6 1 8 1 6 0 0 1 6 01 16 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 l i n e n u m b e r area 0 area 1 w h e n b i t 3 o f o s d c o n t r o l r e g i s t e r 3 i s 0 ( 1 ) c o l o r p a l e t t e s e t b y r c 1 3 t o r c 1 6 o f o s d r a m i s s e l e c t e d c o l o r p a l e t t e 1 ( 9 ) i s s e l e c t e d c o l o r p a l e t t e 2 ( 1 0 ) i s s e l e c t e d color palette 3 (11) is selected color palette 4 (12) is selected 0 1 2 3 4 p l a n e 2 ( c o l o r p a l e t t e s e l e c t i o n b i t 2 ) p l a n e 1 ( c o l o r p a l e t t e s e l e c t i o n b i t 1 ) p l a n e 0 ( c o l o r p a l e t t e s e l e c t i o n b i t 0 ) 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 1 1 1 1 1 1 1 1 1 1 1 1 rev.1.01 2003.07.16 page 85 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp (2) osd ram (addresses 0700 16 to 07a7 16 , 0800 16 to 0fff 16 ) the osd ram for sprite consisting of 3 planes, is assigned to addresses 0700 16 to 07a7 16 . each plane corresponds to each color pallet selection bit and the color pallet of each dot is determined from among 8 kinds. the osd ram for character is allocated at addresses 0800 16 to 0fff 16 , and is divided into a display character code specification part, color code 1 specification part, and color code 2 specification part for each block. tables 8.11.5 and 8.11.6 show the contents of the osd ram. for example, to display 1 character position (the left edge) in block 1, write the character code in address 0800 16 , write color code 1 at 0820 16 , and write color code 2 at 0840 16 . the structure of the osd ram is shown in figure 8.11.23. note : for the layer 2 s osd mode block with dot size of 1.5t c ? ? ? ? ? in osd mode the character is not displayed, and only the left 1/3 part of the 22nd character back ground is displayed in the 22nd s character area. when not displaying this background, set transparent for background. in cdosd mode the character is not displayed, and color pallet color specified by bit 3 to 6 of color code 1 can be output in the 22nd s character area (left 1/3 part). the ram data for the 3nth character does not effect the display. any character data can be stored here (refer to figure 8.11.22). m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 86 of 170 table 8.11.4 contents of osd ram (sprite) line (from top) line 1 line 2 : line 19 line 20 plain 0 (color pallet selection bit 0) 0700 16 0701 16 0702 16 0703 16 : 0724 16 0725 16 0726 16 0727 16 plain 1 (color pallet selection bit 1) 0740 16 0741 16 0742 16 0743 16 : 0764 16 0765 16 0766 16 0767 16 dot (from left) dots 1 to 8 dots 9 to 16 dots 1 to 8 dots 9 to 16 : dots 1 to 8 dots 9 to 16 dots 1 to 8 dots 9 to 16 plain 2 (color pallet selection bit 2) 0780 16 0781 16 0782 16 0783 16 : 07a4 16 07a5 16 07a6 16 07a7 16 b7 b0 b7 781 line 1 783 line 2 7a5 line 19 7a7 line 20 780 782 7a4 7a6 b0 b7 b0 b7 741 line 1 743 line 2 765 line 19 767 line 20 dot number line number 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2 3 4 5 6 7 8 9 10111213141516 740 742 764 766 b0 b7 b0 b7 701 line 1 703 line 2 725 line 19 727 line 20 700 702 724 726 b0 plain 2 plain 1 plain 0 fig. 8.11.22 ram data for 3nth character 1 1 2 2 3 4 4 5 5 7 6 8 7 10 8 11 9 13 10 14 11 16 12 17 13 19 14 20 15 22 16 23 17 25 18 26 19 28 20 29 21 31 22 32 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132 display sequence ram address order display sequence ram address order 1tc size block 1.5tc size block rev.1.01 2003.07.16 page 87 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp display position (from left) 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character block block 1 block 2 block 3 block 4 block 5 block 6 block 7 block 8 block 9 block 10 color code 1 specification 0820 16 0821 16 : 083e 16 083f 16 08a0 16 08a1 16 : 08be 16 08bf 16 0920 16 0921 16 : 093e 16 093f 16 09a0 16 09a1 16 : 09be 16 09bf 16 0a20 16 0a21 16 : 0a3e 16 0a3f 16 0aa0 16 0aa1 16 : 0abe 16 0abf 16 0b20 16 0b21 16 : 0b3e 16 0b3f 16 0ba0 16 0ba1 16 : 0bbe 16 0bbf 16 0c20 16 0c21 16 : 0c3e 16 0c3f 16 0ca0 16 0ca1 16 : 0cbe 16 0cbf 16 color code 2 specification 0840 16 0841 16 : 085e 16 085f 16 08c0 16 08c1 16 : 08de 16 08df 16 0940 16 0941 16 : 095e 16 095f 16 09c0 16 09c1 16 : 09de 16 09df 16 0a40 16 0a41 16 : 0a5e 16 0a5f 16 0ac0 16 0ac1 16 : 0ade 16 0adf 16 0b40 16 0b41 16 : 0b5e 16 0b5f 16 0bc0 16 0bc1 16 : 0bde 16 0bdf 16 0c40 16 0c41 16 : 0c5e 16 0c5f 16 0cc0 16 0cc1 16 : 0cde 16 0cdf 16 character code specification 0800 16 0801 16 : 081e 16 081f 16 0880 16 0881 16 : 089e 16 089f 16 0900 16 0901 16 : 091e 16 091f 16 0980 16 0981 16 : 099e 16 099f 16 0a00 16 0a01 16 : 0a1e 16 0a1f 16 0a80 16 0a81 16 : 0a9e 16 0a9f 16 0b00 16 0b01 16 : 0b1e 16 0b1f 16 0b80 16 0b81 16 : 0b9e 16 0b9f 16 0c00 16 0c01 16 : 0c1e 16 0c1f 16 0c80 16 0c81 16 : 0c9e 16 0c9f 16 table 8.11.5 contents of osd ram (character) m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 88 of 170 block block 11 block 12 block 13 block 14 block 15 block 16 color code 1 specification 0d20 16 0d21 16 : 0d3e 16 0d3f 16 0da0 16 0da1 16 : 0dbe 16 0dbf 16 0e20 16 0e21 16 : 0e3e 16 0e3f 16 0ea0 16 0ea1 16 : 0ebe 16 0ebf 16 0f20 16 0f21 16 : 0f3e 16 0f3f 16 0fa0 16 0fa1 16 : 0fbe 16 0fbf 16 color code 2 specification 0d40 16 0d41 16 : 0d5e 16 0d5f 16 0dc0 16 0dc1 16 : 0dde 16 0ddf 16 0e40 16 0e41 16 : 0e5e 16 0e5f 16 0ec0 16 0ec1 16 : 0ede 16 0edf 16 0f40 16 0f41 16 : 0f5e 16 0f5f 16 0fc0 16 0fc1 16 : 0fde 16 0fdf 16 character code specification 0d00 16 0d01 16 : 0d1e 16 0d1f 16 0d80 16 0d81 16 : 0d9e 16 0d9f 16 0e00 16 0e01 16 : 0e1e 16 0e1f 16 0e80 16 0e81 16 : 0e9e 16 0e9f 16 0f00 16 0f01 16 : 0f1e 16 0f1f 16 0f80 16 0f81 16 : 0f9e 16 0f9f 16 table 8.11.6 contents of osd ram (continued) display position (from left) 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character rev.1.01 2003.07.16 page 89 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp note: do not read from/write to the addresses in table 8.11.7. table 8.11.7 list of access disable addresses 0860 16 to 087f 16 08e0 10 to 08ff 16 0960 16 to 097f 16 09e0 16 to 09ff 16 0a60 16 to 0a7f 16 0ae0 16 to 0aff 16 0b60 16 to 0b7f 16 0be0 16 to 0bff 16 0c60 16 to 0c7f 16 0ce0 16 to 0cff 16 0d60 16 to 0d7f 16 0de0 16 to 0dff 16 0e60 16 to 0e7f 16 0ee0 16 to 0eff 16 0f60 16 to 0f7f 16 0fe0 16 to 0fff 16 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 90 of 170 fig. 8.11.23 structure of osd ram bit rf0 rf1 rf2 rf3 rf4 rf5 rf6 rf7 rc10 rc11 rc12 rc13 rc14 rc15 rc16 rc17 rc20 rc21 bit name function specify character code in osd rom (see note 3) bit name function specify character code in osd rom (see note 3) bit name function specify character code in osd rom (color dot) (see note 4) osd mode cdosd mode notes 1: read value of bits 2 to 7 of the color code 2 is undefined. 2: for not used bits, the write value is read. 3: do not use character code 0ff 16 , 100 16 . 4: do not use character code 1f 16 , 20 16 . 5: refer to figure 8.11.24. 6: only cdosd mode, a dot which selects color pallet 0 or 8 is colored to the color pallet set by rc13 to rc16 of osd ram in character units. cc mode character code (low-order 8 bits) character code (low-order 8 bits) character code (high-order 1 bits) color pallet selection bit 0 color pallet selection bit 1 color pallet selection bit 2 italic control flash control underline control out2 output control color pallet selection bit 0 color pallet selection bit 1 specify color pallet for character (see note 5) 0: italic off 1: italic on 0: flash off 1: flash on 0: underline off 1: underline on 0: out2 output off 1: out2 output on character code (high-order 1 bits) color pallet selection bit color pallet selection bit color pallet selection bit color pallet selection bit 3 color pallet selection bit 0 color pallet selection bit 1 specify color pallet for background (see note 5) specify color pallet for character (see note 5) specify color pallet for background (see note 5) 0: out2 output off 1: out2 output on cd code (6 bits) not used out2 output control not used 0: out2 output off 1: out2 output on blocks 1 to 16 rf6 rf5 rf4 rf3 rf2 rf1 rf0 rc17 rc16 rc15 rc14 rc13 rc12 rc11 rc10 rf7 b0 b7 b0 b7 color code 1 character code color code 2 b0 rc21 rc20 b1 character character background character background character character background color pallet selection bit 0 color pallet selection bit 1 color pallet selection bit 2 color pallet selection bit 3 specify a dot which selects color pallet 0 or 8 by osd rom (see note 6) dot color specify color pallet for background (see note 5) color pallet selection bit 2 color pallet selection bit 3 out2 output control rev.1.01 2003.07.16 page 91 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp 8.11.7 character color as shown in figure 2.11.24, there are 16 built-in color pallets. color pallet 0 is fixed at transparent, and color pallet 8 is fixed at black. the remaining 14 colors can be set to any of the 64 colors available. the setting procedure for character colors is as follows: ?cc mode ................................. 8 kinds color pallet selection range (color pallets 0 to 7 or 8 to 15) can be selected by bit 0 of the osd control register 3 (address 0219 16 ). color pallets are set by bits rc11 to rc13 of the osd ram from among the selection range. ?osd mode .............................. 15 kinds color pallets are set by bits rc11 to rc14 of the osd ram. ?cdosd mode ......................... 8 kinds color pallet selection range (color pallets 0 to 7 or 8 to 15) can be selected by bit 3 of the osd control register 3 (address 0219 16 ). color pallets are set in dot units according to the cd font data (the osd ram m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 92 of 170 fig. 8.11.24 color code selection c o l o r p a l l e t 1 c o l o r p a l l e t 2 c o l o r p a l l e t 3 c o l o r p a l l e t 4 c o l o r p a l l e t 5 c o l o r p a l l e t 6 c o l o r p a l l e t 7 c o l o r p a l l e t 8 ( b l a c k ) c o l o r p a l l e t 9 c o l o r p a l l e t 1 0 c o l o r p a l l e t 1 1 c o l o r p a l l e t 1 2 c o l o r p a l l e t 1 3 c o l o r p a l l e t 1 4 c o l o r p a l l e t 1 5 c o l o r p a l l e t 0 ( t r a n s p a r e n t ) o s d m o d e ( c h a r a c t e r , b a c k g r o u n d ) c c m o d e ( c h a r a c t e r ) s p r i t e d i s p l a y c d o s d m o d e ( c h a r a c t e r ) ( s e e n o t e 2 ) c c m o d e ( b a c k g r o u n d ) a n y c o l o r p a l l e t c a n b e s e l e c t e d . s e l e c t o n e c o l o r p a l l e t i n s c r e e n u n i t s . ( s e e n o t e 1 )( s e e n o t e 1 ) n o t e s 1 : c o l o r p a l l e t s a r e s e l e c t e d b y o s d c o n t r o l r e g i s t e r 3 ( a d d r e s s 0 2 1 9 1 6 ) . 2 : o n l y i n c d o s d m o d e , a d o t w h i c h s e l e c t s c o l o r p a l l e t 0 o r 8 i s c o l o r e d t o o f o s d r a m i n c h a r a c t e r u n i t s . s e l e c t e i t h e r c o l o r p a l l e t i n s c r e e n u n i t s . rev.1.01 2003.07.16 page 93 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.11.26 difference between color code 0 (transparent) and transparent setting of other color codes color pallet 1 (transparent) color pallet 0 (transparent) color pallet 2 (blue) color pallet 8 (black) layer 1 (cc mode) layer 2 (osd mode) when layer 1 has priority. blue transparent (video signal) black 26 dots 20 dots 26 dots 20 dots fig. 8.11.25 set of color pallet 0 or 8 in cdrom mode dot area specified to color pallet 1 dot area specified to color pallet 0 when setting black and blue to color pallets 1 and 2, respectively (only in cdosd mode). set values of osd ram (rc16 to rc13) 0000 transparent black blue 0001 0010 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 94 of 170 fig. 8.11.27 osd control register 3 fig. 8.11.28 color pallet register i (i = 1 to 7, 9 to 15) b7 b6 b5 b4 b3 b2 b1 b0 color pallet register i (cri) (i = 1 to 7, 9to15) [addresses 0241 16 to 0247 16, 0249 16 to 024f 16 ] color pallet register i 0, 1 r signal output control bits (cri0, cri1) indeterminate r w 2, 3 indeterminate r w 4, 5 indeterminate r w indeterminate w 6 7 indeterminate r r g signal output control bits (cri2, cri3) 0 0: no output (see note) 0 1: 1/3 v cc 1 0: 2/3 v cc 11: v cc b0 b1 note: when selecting digital output, the output is v cc at all values other than 00. b signal output control bits (cri4, cri5) out1 signal output control bit (cri6) 0: no output 1: output 0 0: no output (see note) 0 1: 1/3 v cc 1 0: 2/3 v cc 11: v cc b3 b2 0 0: no output (see note) 0 1: 1/3 v cc 1 0: 2/3 v cc 11: v cc b5 b4 b name functions after reset r w nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 osd control register 3 (oc3) [address 0219 16 ] b name functions r w osd control register 3 0 cc mode character color selection bit (oc30) 0 r w 1, 2 0: color code 0 to 7 1: color code 8 to 15 0 r w 30 r w 0 w 4 r cc mode character background color selection bits (oc31, oc32) (see note) 0 0: color code 0 to 3 0 1: color code 4 to 7 1 0: color code 8 to 11 1 1: color code 12 to 15 b1 b1 note: color pallet 8 is always selected for solid space (when out1 output is selected), regardress of value of this register. cdosd mode character color selection bit (oc33) 0: color code 0 to 7 1: color code 8 to 15 sprite color selection bit (oc34) 0: color code 0 to 7 1: color code 8 to 15 0 w 5 r osd mode window control bit (oc35) 0: window off 1: window on 0 w 6 r cc mode window control bit (oc36) 0: window off 1: window on 0 w 7 r cdosd mode window control bit (oc37) 0: window off 1: window on after reset rev.1.01 2003.07.16 page 95 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 8.11.9 out1, out2 signals the out1, out2 signals are used to control the luminance of the video signal. the output waveform of the out1, out2 signals is controlled by bit 6 of the color code register i (refer to figure 8.11.28), fig. 8.11.29 setting value for controlling out1, out2 and corresponding output waveform bit 2 of the block control register i (refer to figure 8.11.14) and rc17 of osd ram. the setting values for controlling out1, out2 and the corresponding output waveform is shown in figure 12.11.29. note: when out2 signal is output, set bit 6 of osd port control register (refer to figure 8.11.56) to 1. output wave- form (between a to a') h notes 1: this control is only valid in the osd mode. it is invalid in cc/cdosd mode . 2: in the cdosd mode, coloring is performed for each dot. accordingly, out1 outputs to dots which bit 6 (cri6) of the color pallet register i is set to 0. 3: out2 cannot be output in sprite osd. 4: ? is an arbitrary value. l l h l h l h l h l h l h l h l h l h out1 control bit (see note 2) (b6 of color pallet register i) o u t 2 o u t p u t c o n t r o l ( r c 1 7 o f o s d r a m ) b a c k g r o u n d character 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 o u t 2 s i g n a l o u t 1 s i g n a l conditions border output control bit (see note 1) (bit 2 of block control register i) a a ' ? ? ? ? ? ? ? m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 96 of 170 8.11.10 attribute the attributes (flash, underline, italic) are controlled to the character font. the attributes to be controlled are different depending on each mode. cc mode .................... flash, underline, italic for each character osd mode ................. border (all bordered, shadow bordered can be selected) for each block (1) under line the underline is output at the 23rd and 24th lines in vertical di- rection only in the cc mode. the underline is controlled by rc16 of osd ram. the color of underline is the same color as that of the character font. (2) flash the parts of the character font, the underline, and the character background are flashed only in the cc mode. the flash is con- trolled by rc15 of osd ram. the on/off for flash is controlled by bit 3 of the osd control register 1 (refer to figure 8.11.3). when this bit is 0 , only character font and underline flash. when 1 , for a character without solid space output, r, g, b and out1 (all display area) flash, for a character with solid space output, only r, g and b (all display area) flash. the flash cycle bases on the v sync count. rev.1.01 2003.07.16 page 97 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.11.30 example of attribute display (in cc mode) 0 1 (d) under line and italic (pre-divide ratio = 2) color code 1 0 1 ( c ) i t a l i c ( p r e - d i v i d e r a t i o = 1 ) color code 1 0 0 c o l o r c o d e 1 bit 6 (rc16) b i t 4 ( r c 1 4 ) (a) ordinary 10 c o l o r c o d e 1 ( b ) u n d e r l i n e (e) under line and italic and flash 1 bit 6 (rc16) bit 5 (rc15) c o l o r c o d e 1 1 bit 4 (rc14) flash flash f l a s h o f f on o f f o n bit 6 (rc16) b i t 4 ( r c 1 4 ) bit 6 (rc16) bit 4 (rc14) bit 6 (rc16) bit 4 (rc14) m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 98 of 170 fig. 8.11.31 example of italic display 10 0 1 1 0 1 (refer to 8.11.10 notes 5, 6 )(refer to 8.11.10 notes 6, 7 ) r c 1 4 o f o s d r a m n o t e s 1 : t h e d o t t e d l i n e i s t h e b o u n d a r y o f c h a r a c t e r c o l o r . 2 : w h e n b i t 1 o f o s d c o n t r o l r e g i s t e r i s 0 . 2 6 t h c h r a c t e r 32nd character (see note 2) rev.1.01 2003.07.16 page 99 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp (4) border the border is output only in the osd mode. the all bordered (bordering around of character font) and the shadow bordered (bordering right and bottom sides of character font) are selected (refer to figure 8.11.32) by bit 2 of the osd control register 1 (refer to figure 8.11.3). the on/off switch for borders can be controlled in block units by bit 2 of the block control register i (refer to figure 8.11.4). the out1 signal is used for border output. the border color is fixed at color code 8 (block). the border color for each screen is specified by the border color register i. fig. 8.11.32 example of border display fig. 8.11.33 horizontal and vertical size of border the horizontal size (x) of border is 1t c (osd clock cycle divided in the pre-divide circuit) regardless of the character font dot size. however, only when the pre-divide ratio = 2 and character size = 1.5t c , the horizontal size is 1.5t c . the vertical size (y) different depending on the screen scan mode and the vertical dot size of character font. notes 1: the border dot area is the shaded area as shown in figure 8.11.34. 2: when the border dot overlaps on the next character font, the charac- ter font has priority (refer to figure 8.11.35 a). when the border dot overlaps on the next character back ground, the border has priority (refer to figure 8.11.35 b). 3: the border in vertical out of character area is not displayed (refer to figure 8.11.35). all bordered shadow bordered y x 1/2h 1h, 2h, 3h 1/2h, 1h, 2h, 3h 1/2h 1h 1h vertical dot size of character font border dot size scan mode horizontal size (x) vertical size (y) normal scan mode bi-scan mode 1t c (osd clock cycle divided in pre-divide circuit) 1.5t c when selecting 1.5t c for character size. m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 100 of 170 fig. 8.11.34 border area fig. 8.11.35 border priority 16 dot s character font area 20 dots osd mode 1 dot width of border 1 dot width of border character boundary b character boundary a character boundary b rev.1.01 2003.07.16 page 101 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 0 off 1 character display area 0 off 1 character display area 0 off 1 solid space character display area 0 off 1 character display area bit 4 of osd control register 1 bit 3 of osd control register 2 rc17 of osd ram out1 output signal out2 output signal 8.11.11 automatic solid space function this function generates automatically the solid space (out1 or out2 blank output) of the character area in the cc mode. the solid space is output in the following area : any character area except character code 009 16 character area on the left and right sides of the above character this function is turned on and off by bit 4 of the osd control register 1 (refer to figure 8.11.3). and the out1 output or out2 output can be selected by bit 3 of osd control register 2. table 8.11.8 setting for automatic solid space 0 1 fig. 8.11.36 display screen example of automatic solid space note: when selecting out1 as solid space output, character background color with solid space output is fixed to color pallet 8 (black) regardless of setting. 0 character font area character background area 1 character font area character background area 0 solid space area 1 character font area character background area 005 16 009 16 009 16 009 16 006 16 006 16 006 16 when setting the character code 005 16 as the character a, 006 16 as the character b. (osd ram) (display screen) 2nd character no blank output 32nd character 1st character m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 102 of 170 8.11.12 multiline display this microcomputer can ordinarily display 16 lines on the crt screen by displaying 16 blocks at different vertical positions. in addition, it can display up to 16 lines by using osd interrupts. an osd interrupt request occurs at the point at which display of each block has been completed. in other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scan- ning line exceeds the block. the mode in which an osd interrupt occurs is different depending on the setting of the osd control regis- ter 2 (refer to figure 8.11.7). when bit 7 of the osd control register 2 is 0 an osd interrupt request occurs at the completion of layer 1 block display. when bit 7 of the osd control register 2 is 1 an osd interrupt request occurs at the completion of layer 2 block display. fig. 8.11.37 note on occurence of osd interrupt notes 1: an osd interrupt does not occur at the end of display when the block is not displayed. in other words, if a block is set to off display by the display control bit of the block control register i (addresses 00d0 16 to 00df 16 ), an osd interrupt request does not occur (refer to figure 8.11.37 (a)). 2: when another block display appeares while one block is displayed, an osd interrupt request occurs only once at the end of the another block display (refer to figure 8.11.37 (b)). 3: on the screen setting window, an osd interrupt occurs even at the end of the cc mode block (off display) out of window (refer to figure 8.11.37 (c)). (b) (c) block 1 (on display) block 2 (on display) block 3 (on display) block 4 (on display) block 1 (on display) block 2 (on display) block 3 (off display) block 4 (off display) osd interrupt request osd interrupt request osd interrupt request osd interrupt request osd interrupt request osd interrupt request no osd interrupt request block 1 block 2 osd interrupt request osd interrupt request osd interrupt request osd interrupt request block 1 block 2 block 3 on display (osd interrupt request occurs at the end of block display) off display (osd interrupt request does not occur at the end of block display) window no osd interrupt request no osd interrupt request (a) rev.1.01 2003.07.16 page 103 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp 8.11.13 sprite osd function this is especially suitable for cursor and other displays as its func- tion allows for display in any position, regardless of the validity of other osds or display positions. the sprite font is a ram font consisting of 16 horizontal dots ? 20 vertical dots, three planes, and three bits of data per dot. each plane has corresponding color pallet selection bits, and 8 kinds of color pallets can be selected by the plane bit combination (three bits) for each dot. in addition, the selec- tion range (color pallets 0 to 7 and 8 to 15) can be set, per screen, by bit 4 of the osd control register 3. the color pallet is set in dot units according to the selection range and the osd ram (sprite) con- tents from among the selection range. it is possible to arbitrarily add font data by software for the ram font in the sprite font. the sprite osd control register can control sprite display, dot size, interrupt position, and interrupt generation factors for the sprite osd. the display position can also be set independently of the block display by the sprite horizontal position registers and the sprite horizontal vertical position registers. at this time, the horizontal posi- tion is set in 2048 steps in 1t osc units, and the vertical position is set in 1024 steps in 1t h units. when sprite display overlaps with other osds, sprite display is always given priority. however, the sprite display overlaps with the osd which includes out2 output, out2 in the osd is output without masking. notes 1: the sprite osd function cannot output out2. 2: when using sprite osd, do not set hs1 < ?0 16 ?at hs2 = ?0 16 . 3: when using sprite osd, do not set vs = vs = ?0 16 . fig. 8.11.38 sprite osd display example video adjustment tint l + contrast | + color tone | + picture | + brightness | + example of cusor display example of sprite font line 1 line 2 line 19 line 20 ...... do t 1 ...... dot 2 do t 15 dot 16 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 104 of 170 fig. 8.11.39 sprite osd control register b7 b6 b5 b4 b3 b2 b1 b0 sprite osd control register (sc) [address 0258 16 ] b name functions after reset rw sprite osd control register 0 sprite osd control bit (sc0) 0rw b3 b2 0 0: 1tc ? 1/2h 0 1: 1tc ? 1h 1 0: 2tc ? 1h 1 1: 2tc ? 2h 2, 3 dot size selection bits (sc2, sc3) 0rw 4 interrupt occurrence position selection bit (sc4) 0rw 5 0r 1 pre-divide ratio selection bit (sc1) 0: pre-divide ratio 1 1: pre-divide ratio 2 0rw 0: stopped 1: operating 0: after display of horizontal 20 dots 1: after display of horizontal 10 dots or 20 dots notes 1: tc : pre-devided clock period for osd 2: h : h sync x in /4096 sprite interrupt source switch bit (sc5) w 6, 7 0r nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0 . 0: x in /4096 interrupt 1: sprite osd interrupt rev.1.01 2003.07.16 page 105 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.11.40 sprite horizontal position register 1 fig. 8.11.41 sprite horizontal position register 2 b7 b6 b5 b4 b3 b2 b1 b0 sprite horizontal position register 1 (hs1) [address 0256 16 ] b name functions after reset r w sprite horizontal position register 1 0 to 7 horizontal display start position control bits of sprite osd (hs10 tohs17) horizontal display start position (low-order 8 bits) tosc ? (setting value of low-order 3 bits of hs2 ? 16 2 + setting value of high-order 4 bits of hs1 ? 16 1 + setting value of low-order 4 bits of hs1 ? 16 0 ) indeterminate r w notes 1: do not set hs1 < 30 16 at hs2 = 00 16 . 2: t osc is osd oscillation period. 3: hs2 is sprite horizontal position register 2. b7 b6 b5 b4 b3 b2 b1 b0 sprite horizontal position register 2 (hs2) [address 0257 16 ] b name functions after reset rw sprite horizontal position register 2 0 to 2 horizontal display start position control bits of sprite osd (hs20 to hs22) horizontal display start position (high-order 3 bits) t osc ? (setting value of low-order 3 bits of hs2 ? 16 2 + setting value of high-order 4 bits of hs1 ? 16 1 + setting value of low-order 4 bits of hs1 ? 16 0 ) indeterminate rw notes 1: do not set hs1< 30 16 at hs2 = 00 16 . 2: t osc is oscillation period. 3: hs1 is sprite horizontal position register 1. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0r 3 to 7 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 106 of 170 fig. 8.11.42 sprite vertical position register 1 fig. 8.11.43 sprite vertical position register 2 b7 b6 b5 b4 b3 b2 b1 b0 sprite vertical position register 1 (vs1) [address 0254 16 ] b name functions afte reset w sprite vertical position register 1 0 vertical display start position control bits of sprite osd (vs10 to vs17) 1r w 1 to 7 0 vertical display start position (low-order 8 bits) th ? (setting value of low-order 2 bits of vs2 ? 16 2 + setting value of high-order 4 bits of vs1 ? 16 1 + setting value of low-order 4 bits of vs1 ? 16 0 ) notes 1: do not set 00 16 to the vs1 at vs2 = 00 16 . 2: t h is cycle of h sync . 3: vs2 is sprite vertical position register 2. r b7 b6 b5 b4 b3 b2 b1 b0 sprite vertical position register 2 (vs2) [address 0255 16 ] b name functions after reset w sprite vertical position register 2 vertical start position control bits of sprite osd (vs20, vs21) 0r w 0, 1 0 vertical display start position (high-order 2 bits) t h ? (setting value of low-order 2 bits of vs2 ? 16 2 + setting value of high-order 4 bits of vs1 ? 16 1 + setting value of low-order 4 bits of vs1 ? 16 0 ) nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0 . 2 to 7 r notes 1: do not set 00 16 to the vs1 at vs2 = 00 16 . 2: t h is cycle of h sync . 3: vs1 is sprite vertical position register 1. r rev.1.01 2003.07.16 page 107 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 8.11.14 window function the window function can be set windows on-screen, and output osd within only the area where the window is set. the on/off for vertical window function is performed by bit 5 of osd control register 1 and is used to select vertical window function or vertical blank function by bit 6 of osd control register 2. accord- ingly, the vertical window function cannot be used simultaneously with the vertical blank function. the display mode to validate the win- dow function is selected by bits 5 to 7 of osd control register 3. the top boundary is set by top border control registers 1, 2 (tb1, tb2) and the bottom boundary is set by bottom border control registers 1, 2 (bb1, bb2). the on/off for horizontal window function is performed by bit 4 of osd control register 2 and is used interchangeably for the horizontal blank function with bit 5 of osd control register 2. accordingly, the horizontal blank function cannot be used simultaneously with the horizontal window function. the display mode to validate the window function is selected by bits 5 to 7 of osd control register 3. the left boundary is set by left border control registers 1, 2 (lb1, lb2), and the right boundary is set by right border control registers 1, 2 (rb1, rb2). fig. 8.11.44 example of window function (when cc mode is valid) cdosd mode f g hij klmno pqr s t osd mode abcde uvwxy screen cc mode window bottom boundary of window top boundary of window right boundary of window left boundary of window window notes 1: horizontal blank and horizontal window, as well as vertical blank and vertical window can not be used simultaneously. 2: when the window function is on by osd control registers 1 and 2, the window function of out2 is valid in all display mode regardless of setting value of osd control register 3 (bits 5 to 7). for example, even when make the window function valid in only cc mode, the function of out2 is valid in osd and cdosd modes. 3: the sprite display is not effected by the window function. m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 108 of 170 8.11.15 blank function the blank function can output blank (out1) area on all sides (verti- cal and horizontal) of the screen. the on/off for vertical blank function is performed by bit 5 of the osd control register 1 and is used to select vertical window function or vertical blank function by bit 6 of the osd control register 2. ac- cordingly, the vertical blank function cannot be used simultaneously with the vertical window function. the top border is set by the top border control registers 1, 2 (tb1, tb2) and the bottom border is set by the bottom border control registers 1, 2 (bb1, bb2), in 1h units. the on/off for horizontal blank function is performed by bit 4 of the osd control register 2 and is used interchangeably for the horizontal window function with bit 5 of the osd control register 2 . accordingly, the horizontal blank function cannot be used simultaneously with the horizontal window function. the left border is set by the left border control registers 1, 2 (lb1, lb2) and the right border is set by the right border control registers 1, 2 (rb1, rb2), in 1t osc units. the osd output (except raster) in area with blank output is not de- leted. these blank signals are not output in the horizontal/vertical blanking interval. fig. 8.11.45 blank output example (when osd output is b + out1) notes 1: horizontal blank and horizontal window, as well as vertical blank and vertical window cannot be used simultaneously. 2: when all-blocks display is off (bit 0 of osd control register 1 = 0 ), do not use vertical blank. output example of horizontal blank output example of top and vertical blank out1 out1 4 a' a b 4 a a ' b blank output signal in microcomputer blank output signal in microcomputer h l h l h l h l h l h l rev.1.01 2003.07.16 page 109 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.11.46 top border control register 1 fig. 8.11.47 top border control register 2 b7 b6 b5 b4 b3 b2 b1 b0 top border control register 1 (tb1) [address 021c 16 ] b name functions after reset rw top border control register 1 0 to 7 control bits of top border (tb10 to tb17) top border position (low-order 8 bits) t h ? (setting value of low-order 2 bits of tb2 ? 16 2 + setting value of high-order 4 bits of tb1 ? 16 1 + setting value of low-order 4 bits of tb1 ? 16 0 ) indeterminate rw notes 1: do not set 00 16 or 01 16 to the tb1 at tb2 = 00 16 . 2: t h is cycle of h sync . 3: tb2 is top border control register 2. b7 b6 b5 b4 b3 b2 b1 b0 top border control register 2 (tb2) [address 021e 16 ] b name functions after reset r w top border control register 2 0, 1 control bits of top border (tb20 ,tb21) top border position (high-order 2 bits) t h ? (setting value of low-order 2 bits of tb2 ? 16 2 + setting value of high-order 4 bits of tb1 ? 16 1 + setting value of low-order 4 bits of tb1 ? 16 0 ) indeterminate rw notes 1: do not set 00 16 or 01 16 to the tb1 at tb2 = 00 16 . 2: t h is cycle of h sync . 3: tb1 is top border control register 1. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are indeterminate. 2 to 7 indetermin ate r m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 110 of 170 fig. 8.11.48 bottom border control register 1 fig. 8.11.49 bottom border control register 2 b7 b6 b5 b4 b3 b2 b1 b0 bottom border control register 1 (bb1) [address 021d 16 ] b name functions after reset r w bottom border control register 1 0 to 7 control bits of bottom border (bb10 to bb17) bottom border position (low-order 8 bits) t h ? (setting value of low-order 2 bits of bb2 ? 16 2 + setting value of high-order 4 bits of bb1 ? 16 1 + setting value of low-order 4 bits of bb1 ? 16 0 ) indeterminate rw notes 1: set values fit for the following condition: (tb1 + tb2 ? 16 2 ) < (bb1 + bb2 ? 16 2 ). 2: t h is cycle of h sync . 3: bb2 is bottom border control reigster 2. b7 b6 b5 b4 b3 b2 b1 b0 bottom border control register 2 (bb2) [address 021f 16 ] b name functions after reset r w bottom border control register 2 0, 1 control bits of bottom border (bb20, bb21) bottom border position (high-order 2 bits) t h ? (setting value of low-order 2 bits of bb2 ? 16 2 + setting value of high-order 4 bits of bb1 ? 16 1 + setting value of low-order 4 bits of bb1 ? 16 0 ) indeterminate indeterminate rw nothing is assigned. these bits are write disable bits. when these bits are read out, the values are indeterminate. r 2 to 7 notes 1: set values fit for the following condition: (tb1 + tb2 ? 16 2 ) < (bb1 + bb2 ? 16 2 ). 2: t h is cycle of h sync . 3: bb1 is bottom border control reigster 1. rev.1.01 2003.07.16 page 111 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig. 8.11.50 left bordercontrol register 1 fig. 8.11.51 left bordercontrol register 2 b7 b6 b5 b4 b3 b2 b1 b0 left border control register 1 (lb1) [address 0250 16 ] b name functions after reset rw left border control register 1 0 control bits of left border (lb10 to lb17) 1 r w 1 to 7 0 left border position (low-order 8 bits) t osc ? (setting value of low-order 3 bits of lb2 ? 16 2 + setting value of high-order 4 bits of lb1 ? 16 1 + setting value of low-order 4 bits of lb1 ? 16 0 ) notes 1: do not set lb1 = lb2 = 00 16 . 2: set values fit for the following condition: (lb1 + lb2 ? 16 2 ) < (rb1 + rb2 ? 16 2 ). 3: t osc is osd oscillation period. 4: lb2 is left border control register 2. b7 b6 b5 b4 b3 b2 b1 b0 left border controlregister 2 (lb2) [address 0251 16 ] b name functions after reset rw left border control register 2 control bits of left border (lb20 to lb22) 0 r w 0 to 2 0 left borderposition (high-order 3 bits) t osc ? (setting value of low-order 3 bits of lb2 ? 16 2 + setting value of high-order 4 bits of lb1 ? 16 1 + setting value of low-order 4 bits of lb1 ? 16 0 ) nothing is assigned. these bits are write disable bits. when these bits are read out, the values are indeterminate. 3 to 7 r w notes 1: do not set lb1 = lb2 = 00 16 . 2: set values fit for the following condition: (lb1 + lb2 ? 16 2 ) < (rb1 + rb2 ? 16 2 ). 3: t osc is osd oscillation period. 4: lb1 is left border control register 1. m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 112 of 170 fig. 8.11.52 right border control register 1 fig. 8.11.53 right border control register 2 b7 b6 b5 b4 b3 b2 b1 b0 right border control register 1 (rb1) [address 0252 16 ] b name functions after reset rw right border control register 1 control bits of right border (rb10 to rb17) 1 rw 0 to 7 right border position (low-order 8 bits) t osc ? (setting value of low-order 3 bits of rb2 ? 16 2 + setting value of high-order 4 bits of rb1 ? 16 1 + setting value of low-order 4 bits of rb1 ? 16 0 ) notes 1: set values fit for the following condition: (lb1 + lb2 ? 16 2 ) < (rb1 + rb2 ? 16 2 ). 2: t osc is osd oscillation period. 3: rb2 is right border control register 2. b7 b6 b5 b4 b3 b2 b1 b0 right border control register 2 (rb2) [address 0253 16 ] b name functions after reset rw right border control register 2 control bits of right border (rb20 to rb22) 1 r w 0 to 2 0 right border position (high-order 3 bits) t osc ? (setting value of low-order 3 bits of rb2 ? 16 2 + setting value of high-order 4 bits of rb1 ? 16 1 + setting value of low-order 4 bits of rb1 ? 16 0 ) nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0 . 3 to 7 r w notes 1: set values fit for the following condition: (lb1 + lb2 ? 16 2 ) < (rb1 + rb2 ? 16 2 ). 2: t osc is osd oscillation period. 3: rb1 is right border control register 1. rev.1.01 2003.07.16 page 113 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 8.11.16 raster coloring function an entire screen (raster) can be colored by setting the bits 6 to 0 of the raster color register. since each of the r, g, b, out1, and out2 pins can be switched to raster coloring output, 64 raster colors can be obtained. when the character color/the character background color overlaps with the raster color, the color (r, g, b, out1, out2),specified for the character color/the character background color, takes priority of the raster color. this ensures that the character color/the character background color is not mixed with the raster color. the raster color register is shown in figure 8.11.54, the example of raster coloring is shown in figure 8.11.55. fig. 8.11.54 raster color register b7 b6 b5 b4 b3 b2 b1 b0 raster color register (rc) [address 0218 16 ] b name functions at reset r w raster color register 0, 1 raster color r control bits (rc0, rc1) 0 r w 2, 3 0 r w 4, 5 0 r w 0 0 w 6 70 r w r raster color g control bits (rc2, rc3) 0 0: no output (see note) 0 1: 1/3 v cc 1 0: 2/3 v cc 1 1: v cc b0 b1 note: when selecting digital output, v cc is output at any other values except 00. raster color b control bits (rc4, rc5) raster color out1 control bits (rc6) 0: no output 1: output 0 0: no output (see note) 0 1: 1/3 v cc 1 0: 2/3 v cc 1 1: v cc b3 b2 0 0: no output (see note) 0 1: 1/3 v cc 1 0: 2/3 v cc 1 1: v cc b5 b4 raster color out2 control bits (rc7) 0: no output 1: output note : raster is not output to the area which includes blank output. m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 114 of 170 fig. 8.11.55 example of raster coloring h s y n c a' a o u t 1 r g b h s y n c a ' a o u t 1 r g b : character color red (r + out1) : border color black (out1) : background color magenta (r + b + out1) : raster color blue (b + out1 + out2) s i g n a l s a c r o s s a - a ' b l a n k c o n t r o l s i g n a l i n m i c r o c o m p u t e r : horizontal blank (out1) : c h a r a c t e r c o l o r r e d ( r + o u t 1 ) : b o r d e r c o l o r b l a c k ( o u t 1 ) : b a c k g r o u n d c o l o r m a g e n t a ( r + b + o u t 1 ) : r a s t e r c o l o r b l u e ( b + o u t 1 + o u t 2 ) signals across a-a' < a t h o r i z o n t a l b l a n k o u t p u t > o u t 2 o u t 2 rev.1.01 2003.07.16 page 115 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 8.11.17 scan mode this microcomputer has the bi-scan mode for corresponding to h sync of double speed frequency. in the bi-scan mode, the vertical start display position and the vertical size is two times as compared with the normal scan mode. the scan mode is selected by bit 1 of the osd control register 1 (refer to figure 8.11.3). scan mode parameter bit 1 of osd control register 1 vertical display start position vertical dot size table 8.11.9 setting for scan mode normal scan 0 value of vertical position register ? 1h 1t c ? 1/2h 1t c ? 1h 2t c ? 2h 3t c ? 3h bi-scan 1 value of vertical position register ? 2h 1t c ? 1h 1t c ? 2h 2t c ? 4h 3t c ? 6h m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 116 of 170 8.11.18 osd output pin control the osd output pins r(r1), g(g1), b(b1) and out1 can also func- tion as ports p5 2 to p5 5 . set the corresponding bit of the osd port control register (address 00cb 16 ) to 0 to specify these pins as osd output pins, or set it to 1 to specify it as a general-purpose port p5 pin. pins r0, g0 and b0 can also function as ports p1 7 , p1 5 and p1 6 , respectively. set bit 1 of the osd port control register to 0 to specify these pins as a general-purpose output port p1 pin, or set it to 1 to specify it as osd output pins. when 0, 4-adjustment-level analog output is output from pins r, g and b. when 1, the value which is converted from the analog to the 2-bit digital is output as follows: the high-order bit is output pins r1, g1 and b1 and the low-order bit is output from pins r0, g0 and b0. the out2 can also function as port p1 0 . set bit 0 of the port p1 direction register (address 00c3 16 ) to 1 (output mode). after that, set bit 6 of the osd port control register to 1 to specify the pin as osd output pin, or set it to 0 to specify as port p1 0 pin. the input polarity of the h sync , v sync and output polarity of signals r, g, b, out1 and out2 can be specified with the i/o polarity con- trol register (address 0217 16 ). set a bit to 0 to specify positive polarity; set it to 1 to specify negative polarity (refer to figure 8.11.18). the osd port control register is shown in figure 8.11.56. fig. 8.11.56 osd port control register b7 b6 b5 b4 b3 b2 b1 b0 osd port control register (pf) [address 00cb 16 ] b name functions after reset r w osd port control register 00 r w fix this bit to 0 00 2 0 : r signal output 1 : port p5 2 output 0 r w 3 port p5 3 output signal selection bit (g) 0 : g signal output 1 : port p5 3 output 0 r w 4 port p5 4 output signal selection bit (b) 0 : b signal output 1 : port p5 4 output 0 r w 5 port p5 5 output signal selection bit (out1) 0 : out1 signal output 1 : port p5 5 output 0 r w 6 port p1 0 output signal selection bit (out2) 0 : port p1 0 signal output 1 : out2 output 0 r w port p5 2 output signal selection bit (r) 70 r w fix this bit to 0 1 0 : 4-adjustment-level analog is output from pins r, g, b. 1 : value which is converted from 4-adjustment-level analog to 2-bit digital is output as below: high-order: from r1, g1, b1 low-order: from r0, g0, b0 0 r w r, g, b output method selection bit (rgb2bit) note: when using ports p5 2 to p5 4 as general-purpose pins, set bit 2 of osd control register 2 (address 0215 16 ) to 0. rev.1.01 2003.07.16 page 117 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp fig.8.12.1 sequence at detecting software runaway detection 8.12. software runaway detect func- tion this microcomputer has a function to decode undefined instructions to detect a software runaway. when an undefined op-code is input to the cpu as an instruction code during operation, the following processing is done. ? the cpu generates an undefined instruction decoding signal. ? the device is internally reset because of occurrence of the unde- fined instruction decoding signal. ? as a result of internal reset, the same reset processing as in the case of ordinary reset operation is done, and the program restarts from the reset vector. note, however, that the software runaway detecting function cannot be invalid. ad h , ad l 01,s 2 01,s 1 pc h pc l ps ad h ad l pc ? ? : undefined instruction decode ? undefined instruction decoding signal occurs.internal reset signal occurs. sync address data reset sequence 01,s fffe 16 ffff 16 : invalid : program counter s : stack pointer pc ad l , ad h : jump destination address of reset m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 118 of 170 8.13. reset circuit when the oscillation of a quartz-crystal oscillator or a ceramic reso- nator is stable and the power source voltage is 5 v 10 %, hold the reset pin at low for 2 s or more, then return is to high. then, as shown in figure 8.13.2, reset is released and the program starts form the address formed by using the content of address ffff 16 as the high-order address and the content of the address fffe 16 as the low-order address. the internal state of microcomputer at reset are shown in figures 8.2.4 to 8.2.9. an example of the reset circuit is shown in figure 8.13.1. the reset input voltage must be kept 0.9 v or less until the power source voltage surpasses 4.5 v. fig.8.13.2 reset sequence fig.8.13.1 example of reset circuit p o w e r s o u r c e v o l t a g e 0 v r e s e t i n p u t v o l t a g e 0 v 4.5 v 0.9 v p o w e r o n v c c r e s e t vss microcomputer 1 5 4 3 0.1 f m 5 1 9 5 3 a l x in reset internal reset sync address data 32768 count of x in clock cycle (note 3) reset address from the vector table ? ? 01, s 01, s-1 01, s-2 fffe ffff ad h , ad l ? ? ? ? ? ad l ad h notes 1 : f(x in ) and f( ) are in the relation : f(x in ) = 2 f ( ). 2 : a question mark (?) indicates an undefined state that depends on the previous state. 3 : immediately after a reset, timer 3 and timer 4 are connected by hardware. at this time, ff 16 is set in timer 3 and 07 16 is set to timer 4. timer 3 counts down with f(x in )/16, and reset state is released by the timer 4 overflow signal. rev.1.01 2003.07.16 page 119 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 8.14 clock generating circuit this microcomputer has 2 built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturer s recommended values. no external re- sistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . when using x cin -x cout as sub-clock, clear bits 5 and 4 of the clock source control register to 0. to supply a clock signal externally, input it to the x in (x cin ) pin and make the x out (x cout ) pin open. when not using x cin clock, connect the x cin to v ss and make the x cout pin open. after reset has completed, the internal clock is half the frequency of x in . immediately after poweron, both the x in and x cin clock start oscillating. to set the internal clock to low-speed operation mode, set bit 7 of the cpu mode register (address 00fb 16 ) to 1. 8.14.1 oscillation control (1) stop mode when the stp instruction is executed, the internal clock stops at high. at the same time, timers 3 and 4 are connected by hardware and ff 16 is set in timer 3 and 07 16 is set in timer 4. select f(x in )/ 16 or f(x cin )/16 as the timer 3 count source (set both bit 0 of the timer mode register 2 and bit 6 at address 00c7 16 to 0 before the execution of the stp instruction). moreover, set the timer 3 and timer 4 interrupt enable bits to disabled ( 0 ) before execution of the stp instruction. the oscillator restarts when external interrupt is accepted. however, the internal clock keeps its high level until timer 4 over- flows, allowing time for oscillation stabilization when a ceramic reso- nator or a quartz-crystal oscillator is used. (2) wait mode when the wit instruction is executed, the internal clock stops in the high level but the oscillator continues running. this wait state is released at reset or when an interrupt is accepted (note). since the oscillator does not stop, the next instruction can be executed at once. note: in the wait mode, the following interrupts are invalid. v sync interrupt osd interrupt all timers interrupts using external clock from port pin input as count source all timer interrupts using f(x in )/2 or f(x cin )/2 as count source all timer interrupts using f(x in )/4096 or f(x cin )/4096 as count source f(x in )/4096 interrupt multi-master i 2 c-bus interface interrupt data slicer interrupt a-d conversion interrupt sprite osd interrupt fig.8.14.1 ceramic resonator circuit example fig.8.14.2 external clock input circuit example (3) low-speed mode if the internal clock is generated from the sub-clock (x cin ), a low power consumption operation can be realized by stopping only the main clock x in . to stop the main clock, set bit 6 (cm6) of the cpu mode register (00fb 16 ) to 1. when the main clock x in is restarted, the program must allow enough time to for oscillation to stabilize. note that in low-power-consumption mode the x cin -x cout drivability can be reduced, allowing even lower power consumption. to reduce the x cin -x cout drivability, clear bit 5 (cm5) of the cpu mode regis- ter (00fb 16 ) to 0. at reset, this bit is set to 1 and strong drivability is selected to help the oscillation to start. when an stp instruction is executed, set this bit to 1 by software before executing. x cin x in c cin microcomputer x cout r f r d c cout x out c in c ou t x cin microcomputer external oscillation circuit or external pulse x cout x in x out open open external oscillation circuit vcc vss vcc vss m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 120 of 170 fig.8.14.3 clock generating circuit block diagram x cin x cout osc1 oscillating mode selection bits (see notes 1, 4) internal system clock selection bit (see notes 1, 3) internal system clock selection bit (notes 1, 3) main clock (x in x out ) stop bit (notes 1, 3) r s q stp instruction wit instruction r s q reset interrupt disable flag i interrupt request r s q reset stp instruction timing (internal clock) timer 3 count source selection bit (see notes 1, 2) 1 timer 3 count stop bit (see notes 1, 2) timer 4 count stop bit (see notes 1, 2) timer 3 timer 4 1/2 1/8 x out x in 1 0 0 notes 1 : the value at reset is 0. 2: refer to timer mode register 2. 3: refer to cpu mode register (next page). 4: refer to clock source control register. rev.1.01 2003.07.16 page 121 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp fig.8.14.4 state transitions of system clock reset the example assumes that 8 mhz is being applied to the x in pin and 32 khz to the x cin pin. the indicates the internal clock. wit instruction cm7 : internal system clock selection bit 0 : x in -x out selected (high-speed mode) 1 : x cin -x cout selected (low-speed mode) cpu mode register (address : 00fb 16 ) cm6 : main clock (x in x out ) stop bit 0 : oscillating 1 : stopped 8 mhz oscillating 32 khz oscillating is stopped (high) timer operating 8 mhz oscillating 32 khz oscillating f( ) = 4 mhz 8 mhz stopped 32 khz stopped is stopped (high) 8 mhz oscillating 32 khz oscillating is stopped (high) timer operating (note 3) 8 mhz oscillating 32 khz oscillating f( ) = 16 khz 8 mhz stopped 32 khz stopped is stopped (high) 8 mhz stopped 32 khz stopped = stopped (high ) 8 mhz stopped 32 khz oscillating f( ) = 16 khz 8 mhz stopped 32 khz oscillating is stopped (high) timer operating (note 3) interrupt stp instruction interrupt (note 1) wit instruction interrupt wit instruction interrupt stp instruction interrupt (note 2) stp instruction interrupt (note 2) cm7 = 1 cm7 = 0 cm6 = 1 cm6 = 0 external int, timer interrupt, or si/o interrupt external int notes 1: when the stp state is ended, a delay of approximately 4 ms is automatically generated by timer 3 and timer 4. 2: the delay after the stp state ends is approximately 1 s. 3: when the internal clock divided by 8 is used as the timer count source, the frequency of the count source is 2 khz. the program must allow time for 8 mhz oscillation to stabilize high-speed operation start mode m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 122 of 170 reset vss vcc circuit example 1 reset vss vcc circuit example 2 note : make the level change from l to h at the point at which the power source voltage exceeds the specified voltage. 8.15. display oscillation circuit the osd oscillation circuit has a built-in clock oscillation circuits, so that a clock for osd can be obtained simply by connecting an lc, a ceramic resonator, or a quartz-crystal oscillator across the pins osc1 and osc2. which of the sub-clock or the osd oscillation circuit is selected by setting bits 5 and 4 of the clock control register (address 0216 16 ). 8.17. addressing mode the memory access is reinforced with 17 kinds of addressing modes. refer to series 740 rev.1.01 2003.07.16 page 123 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp power source voltage v cc , (see note 1) input voltage cnv ss input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 , p3 1 , p4 0 ?4 6 , p6 4 , p6 3 , p7 0 ?7 2 , x in , h sync , v sync , ______ reset output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 , p3 1 , p5 2 ?5 5 , s out , s clk , x out , osc2 circuit current p5 2 ?5 5 , p1 0 , p0 3 , p1 5 ?1 7 , p2 0 ?2 7 , p3 0 , p3 1 circuit current p5 2 ?5 7 , p1 0 , p0 3 , p1 5 ?1 7 , p2 0 ?2 7 , p6 5 ?6 7 , s out , s clk circuit current p1 1 ?1 4 circuit current p0 0 ?0 2 , p0 4 ?0 7 circuit current p3 0 , p3 1 power dissipation operating temperature storage temperature symbol v cc , (av cc ) v i v i v o i oh i ol1 i ol2 i ol3 i ol4 p d t opr t stg 10. absolute maximum ratings conditions all voltages are based on v ss . output transistors are cut off. parametear t a = 25 ? unit v v v v ma ma ma ma ma mw ? ? ratings ?.3 to 6 ?.3 to 6 ?.3 to v cc + 0.3 ?.3 to v cc + 0.3 0 to 1 (see note 2) 0 to 2 (see note 3) 0 to 6 (see note 3) 0 to 1 (see note 3) 0 to 10 (see note 4) 550 ?0 to 70 ?0 to 125 power source voltage (see note 1, 5), during cpu, osd, data slicer operation ram hold voltage (when clock is stopped) power source voltage high input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 , p3 1, p4 0 ?4 6 , p6 3 , p6 4 , p7 0 ?7 2 , h sync , v sync , reset, x in high input voltage scl1, scl2, sda1, sda2 low input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 , p3 1, p4 0 ?4 6 , p6 3 , p6 4 , p7 0 ?7 2 low input voltage scl1, scl2, sda1, sda2 low input voltage (see note 7) reset, x in , osc1, h sync , v sync , int1?nt3, tim2, tim3, s clk , s in high average output current (see note 2) p5 2 ?5 5 , p1 0 , p0 3 , p1 5 ?1 7 , p2 0 ?2 7 , p3 0 , p3 1 low average output current (see note 3) p5 1 ?5 5 , p1 0 , p0 3 , p1 5 ?1 7 , p2 0 ?2 7 , s out , s clk low average output current (see note 3) p1 1 ?1 4 low average output current (see note 3) p0 0 ?0 2 , p0 4 ?0 7 low average output current (see note 4) p3 0 , p3 1 oscillation frequency (for cpu operation) (see note 6) x in oscillation frequency (for sub-clock operation) x cin oscillation frequency (for osd) osc1 load resistance during r,g,b analog output input frequency tim2, tim3, int1?nt3 input frequency s clk input frequency scl1, scl2 input frequency horizontal sync. signal of video signal input amplitude video signal cv in limits min. 4.5 2.0 0 0.8v cc 0.7v cc 0 0 0 7.9 29 11.0 25.5 20.0 15.262 1.5 typ. 5.0 0 8.0 32 26.5 15.734 2.0 max. 5.5 5.5 0 v cc v cc 0.4 v cc 0.3 v cc 0.2 v cc 1 2 6 1 10 8.1 35 27.0 27.5 100 1 400 16.206 2.5 v v v v v v v v ma ma ma ma ma mhz khz mhz khz mhz khz khz v 11. recommended operating conditions (t a = ?0 ? to 70 ?, v cc = 5 v ?10 %, unless otherwise noted) v cc , (av cc ) v cc , (av cc ) v ss v ih1 v ih2 v il1 v il2 v il3 i oh i ol1 i ol2 i ol3 i ol4 f(x in ) f(x cin ) fosc r l f hs1 f hs2 f hs3 f hs4 v i symbol parameter unit lc oscillating mode ceramic oscillating mode m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 124 of 170 power source current high output voltage p5 2 ?5 5 , p1 0 , p0 3 , p1 5 ?1 7 , p2 0 ?2 7 , p3 0 , p3 1 low output voltage s out , s clk , p0 0 ?0 7 , p1 0 , p1 5 ?1 7 , p2 0 ?2 7 ,p3 2 , p4 7 , p5 0 ?5 7 , p6 0 ?6 2 , p6 5 ?6 7 low output voltage p3 0 , p3 1 low output voltage p1 1 ?1 4 hysteresis (see note 6) reset, h sync , v sync , int1,int2, int3, tim2, tim3, s in , s clk , scl1, scl2, sda1, sda2 high input leak current reset, p0 0 ?0 7 , p1 0 ?1 7 , p2 0 p2 7 , p3 0 , p3 1 , p4 0 ?4 6 , p6 3 , p6 4 , p7 0 ?7 2 , h sync , v sync low input leak current reset, p0 0 ?0 7 , p1 0 ?1 7 , p2 0- p2 7 , p3 0 , p3 1 , p4 0 ?4 6 , p6 3 , p6 4 , p7 0 ?7 2 , h sync , v sync i 2 c-bus?us switch connection resistor (between scl1 and scl2, sda1 and sda2) max. 30 50 70 200 4 100 10 0.4 3.0 0.4 0.6 1.3 5 5 130 limits min. 2.4 12. electric characteristics (v cc = 5 v ?10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = ?0 ? to 70 ?, unless otherwise noted) i cc v oh v ol v t+ ?v t i izh i zl r bs typ. 15 30 50 60 2 25 1 0.5 symbol parameter test conditions unit system operation wait mode stop mode v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 32 khz, osd off, data slicer off, low-power dissipation mode set (cm5 = ?? cm6 = ?? v cc = 5.5 v, f(x in ) = 8 mhz v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 32khz, low-power dissipation mode set (cm5 = ?? cm6 = ?? v cc = 5.5 v, f(x in ) = 0 f(x cin ) = 0 v cc = 4.5 v i oh = ?.5 ma v cc = 4.5 v i ol = 0.5 ma v cc = 4.5 v i ol = 10.0 ma v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v i = 5.5 v v cc = 5.5 v v i = 0 v v cc = 4.5 v crt off data slicer off crt on (digital output) data slicer on crt on (analog output) data slicer on test circuit v cc = 5.5 v, f(x in ) = 8 mhz ma a ma a v v v v a ma ? 1 2 2 3 4 5 notes 1: the total current that flows out of the ic must be 20 or less. 2: the total input current to ic (i ol1 + i ol2 + i ol3 ) must be 20 ma or less. 3: the total average input current for ports p3 0 , p3 1 to ic must be 10 ma or less. 4: connect 0.1 f or more capacitor externally between the power source pins v cc ? ss (and av cc ? ss ) so as to reduce power source noise. also connect 0.1 f or more capacitor externally between the pins v cc ?nv ss . ( ) ... m37280eksp 5: use a quartz-crystal oscillator or a ceramic resonator for the cpu oscillation circuit. when using the data slicer, use 8 mhz. 6: p1 6 , p4 1 ?4 4 have the hysteresis when these pins are used as interrupt input pins or timer input pins. p1 1 ?1 4 have the hysteresis when these pins are used as multi-master i 2 c-bus interface ports. p1 7 , p4 6 and p7 2 have the hysteresis when these pins are used as serial i/o pins. 7: when using the sub-clock, set f clk < f cpu /3. 8: pin names in each parameter is described as below. (1) dedicated pins: dedicated pin names. (2) duble-/triple-function ports ?when the same limits: i/o port name. ?when the limits of functins except ports are different from i/o port limits: function pin name. i ol = 3 ma i ol = 6 ma rev.1.01 2003.07.16 page 125 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp fig.12.1 test circuit 1 3 2 4 5 vss vcc v v oh or or v ol i oh i ol 4.5v each output pin after setting each output pin to high level when measuring v oh and to low level when measuring v ol , each pin is measured. vss vcc 5.0v each output pin vss vcc v bs 4.5v scl1 or sda1 i bs a r bs = v bs /i bs scl2 or sda2 r bs a vss vcc x cin x cout x in x out osc1 osc2 icc 8.00 mhz 32 khz power source voltage pin v cc is confirmed the operation and tested the current with a ceramic resonator. vss vcc i izh or i izl 5.5v a 5.5v or 0v each output pin m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 126 of 170 14. a-d converter characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = 10 c to 70 c, unless otherwise noted) resolution absolute accuracy (excludig guantization error) conversion time ladder resistor analog input voltage max. 8 ?.5 12.5 v ref bits lsb ? t conv r ladder v ia vcc = 5 v 13. analog r, g, b output characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = 10 c to 70 c, unless otherwise noted) symbol r o v oe t st parameter test conditions limits min. typ. unit k ? ? fig.13.1 analog r, g, b, output characteristics v cc v 0e v p-p v 0e t st 70%v p-p 30%v p-p 2/3v cc 1/3v cc v ss rev.1.01 2003.07.16 page 127 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 15. multi-master i 2 c-bus bus line characteristics bus free time hold time for start condition low period of scl clock rising time of both scl and sda signals data hold time high period of scl clock falling time of both scl and sda signals data set-up time set-up time for repeated start condition set-up time for stop condition t buf t hd; sta t low t r t hd; dat t high t f t su; dat t su; sta t su; sto max. 1000 300 min. 1.3 0.6 1.3 20+0.1c b 0 0.6 20+0.1c b 100 0.6 0.6 max. 300 0.9 300 note: c b = total capacitance of 1 bus line fig.15.1 definition diagram of timing on multi-master i 2 c-bus min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 sda scl p t buf s t hd ; sta t low t r t hd ; dat t high t f t su ; dat t su ; sta sr p t su ; sto t hd ; sta s sr p : start condition : restart condition : stop condition m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 128 of 170 16. prom programming method the built-in prom of the one time prom version (blank) and the built-in eprom version can be read or programmed with a general- purpose prom programmer using a special programming adapter. product m37281eksp name of programming adapter pca7400 the prom of the one time prom version (blank) is not tested or screened in the assembly process nor any following processes. to ensure proper operation after programming, the procedure shown in figure 16.1 is recommended to verify programming. fig. 16.1 programming and testing of one time prom version programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer functional check in target device caution : the screening temperature is far higher than the storage temperature. never expose to 150 c exceeding 100 hours. rev.1.01 2003.07.16 page 129 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp 17. data required for mask orders the following are necessary when ordering a mask rom produc- tion: mask rom order confirmation form mark specification form data to be written to rom, in eprom form (52-pin dip type 27c101, three identical copies) or fdk m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 130 of 170 18. appendix pin configuration (top view) outline 52p4b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 hlf/ad6 h sync v sync p4 0 /ad4 p4 1 /int2 p4 2 /tim2 p4 3 /tim3 p2 4 /ad3 p2 5 /ad2 p0 1 /pwm5 p0 2 /pwm6 p1 7 /s in /r0 p4 4 /int1 p4 6 /s clk p7 2 /(s in ) p5 2 /r/r1 p5 3 /g/g1 p5 4 /b/b1 p5 5 /out1 p0 4 /pwm0 p0 5 /pwm1 p1 0 /out2 p1 1 /scl1 p1 2 /scl2 p1 3 /sda1 p1 4 /sda2 p1 5 /g0 p1 6 /int3/b0 p3 0 /ad7 p3 1 /ad8 reset p6 4 /osc2/x cout p6 3 /osc1/x cin v cc p0 3 /pwm7 p2 6 /ad1 p2 7 /ad5 p0 0 /pwm4 p4 5 /s out p0 6 /pwm2 p2 1 p2 2 p2 3 17 18 19 20 37 36 35 34 33 m37281mah-xxxsp, M37281MFH-XXXSP, m37281mkh-xxxsp, m37281eksp p7 0 /cv in p7 1 /v hold cnv ss x out x in v ss 21 22 23 24 25 26 32 31 30 29 28 27 p0 7 /pwm3 p2 0 ( )...m37281eksp (av cc ) nc note : only 18th pin is nc pin of m37281mah/ mfh/mkh-xxxsp. this pin is avcc pin of m37281eksp. but nc pin of m37281mah/mfh/mkh-xxxsp is not connect in the ic. you can apply to vcc. rev.1.01 2003.07.16 page 131 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp memory map 0 0 0 0 1 6 0 0 c 0 1 6 0 0 f f 1 6 0 f f f 1 6 f f f f 1 6 f f d e 1 6 f f 0 0 1 6 0 8 0 0 1 6 1 0 8 0 0 1 6 1 f f f f 1 6 r o m ( 6 0 k b y t e s ) o s d r a m ( c h a r a c t e r ) ( 1 5 3 6 b y t e s ) ( n o t e 2 ) 0 2 0 0 1 6 0 2 5 8 1 6 1 0 0 0 1 6 1 5 7 f f 1 6 1 8 0 0 0 1 6 1 0 0 0 0 1 6 s f r 1 a r e a s f r 2 a r e a n o t e s 1 : r e f e r t o t a b l e 8 . 1 1 . 6 o s d r a m ( s p r i t e ) . 2 : t a b l e s 8 . 1 1 . 4 a n d 8 . 1 1 . 5 o s d r a m ( c h a r a c t e r ) . 0 2 c 0 1 6 0 2 e 0 1 6 0 1 0 0 1 6 0 0 b f 1 6 0 7 0 0 1 6 0 7 a 7 1 6 o s d r a m ( s p r i t e ) ( 1 2 0 b y t e s ) ( n o t e 1 ) 1 a c f f 1 6 0 6 f f 1 6 r a m ( 1 5 3 6 b y t e s ) 1 b 0 0 0 1 6 1 c 0 0 0 1 6 1 d 0 0 0 1 6 1 e 0 0 0 1 6 1 f 0 0 0 1 6 2 0 0 0 1 6 m 3 7 2 8 1 m k h - x x x s p , m 3 7 2 8 1 e k s p n o t u s e d n o t u s e d z e r o p a g e e x t r a a r e a i n t e r r u p t v e c t o r a r e a s p e c i a l p a g e r o m c o r r e c t i o n f u n c t i o n v e c t o r 1 : a d d r e s s 0 2 c 0 1 6 v e c t o r 2 : a d d r e s s 0 2 e 0 1 6 o s d r o m ( c h a r a c t e r f o n t ) ( 2 0 4 0 0 b y t e s ) n o t u s e d n o t u s e d o s d r o m ( c o l o r d o t f o n t ) ( 9 6 7 2 b y t e s ) n o t u s e d e x p a n s i o n r o m ( 2 0 k b y t e s ) b a n k 1 1 b a n k 1 2 b a n k 1 3 b a n k 1 4 b a n k 1 5 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 132 of 170 0 0 0 0 1 6 0 0 c 0 1 6 00ff 16 0 f f f 1 6 ffff 16 f f d e 1 6 ff00 16 0 8 0 0 1 6 1 0 8 0 0 1 6 0 2 0 0 1 6 0 2 5 8 1 6 1000 16 1 5 7 f f 1 6 1 8 0 0 0 1 6 1 0 0 0 0 1 6 0 2 c 0 1 6 0 2 e 0 1 6 0100 16 00bf 16 0 7 0 0 1 6 0 7 a 7 1 6 1acff 16 0 5 3 f 1 6 m 3 7 2 8 1 m ah- x x x s p, rom (60k bytes) osd ram (character) (1536 bytes) (note 2) s f r 1 a r e a s f r 2 a r e a n o t e s 1 : r e f e r t o t a b l e 8 . 1 1 . 6 o s d r a m ( s p r i t e ) . 2 : t a b l e s 8 . 1 1 . 4 a n d 8 . 1 1 . 5 o s d r a m ( c h a r a c t e r ) . o s d r a m ( s p r i t e ) ( 1 2 0 b y t e s ) ( n o t e 1 ) ram (1088 bytes) n o t u s e d n o t u s e d z e r o p a g e e x t r a a r e a interrupt vector area special page rom correction function vector 1: address 02c0 16 vector 2: address 02e0 16 o s d r o m ( c h a r a c t e r f o n t ) ( 2 0 4 0 0 b y t e s ) not used not used osd rom (color dot font) (9672 bytes) not used 6000 16 rom (40k bytes) M37281MFH-XXXSP m37281mah-xxxsp, M37281MFH-XXXSP M37281MFH-XXXSP m37281mah-xxxsp rev.1.01 2003.07.16 page 133 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp memory map of special function register (sfr) d 0 1 6 d 1 1 6 d2 16 d 3 1 6 d 4 1 6 d 5 1 6 d6 16 d 7 1 6 d 8 1 6 d9 16 d a 1 6 d b 1 6 dc 16 d d 1 6 d e 1 6 d f 1 6 c0 16 c 1 1 6 c2 16 c 3 1 6 c4 16 c5 16 c6 16 c 7 1 6 c 8 1 6 c9 16 c b 1 6 c c 1 6 c d 1 6 ce 16 c f 1 6 ca 16 a d d r e s s p o r t p 5 ( p 5 ) osd control register 1 (oc 1) h o r i z o n t a l p o s i t i o n r e g i s t e r ( h p ) b l o c k c o n t r o l r e g i s t e r 1 ( b c 1 ) port p1 (p1) port p1 direction register (d1) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( d 3 ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( d 2 ) registe r p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( d 0 ) block control register 2 (bc 2 ) b l o c k c o n t r o l r e g i s t e r 3 ( b c 3 ) b l o c k c o n t r o l r e g i s t e r 4 ( b c 4 ) b l o c k c o n t r o l r e g i s t e r 5 ( b c 5 ) b l o c k c o n t r o l r e g i s t e r 6 ( b c 6 ) b l o c k c o n t r o l r e g i s t e r 7 ( b c 7 ) bit allocation state immediately after rese t p o r t p 4 ( p 4 ) port p4 direction register (d4) o s d p o r t c o n t r o l r e g i s t e r ( p f ) port p6 (p6) b l o c k c o n t r o l r e g i s t e r 8 ( b c 8 ) b l o c k c o n t r o l r e g i s t e r 9 ( b c 9 ) b l o c k c o n t r o l r e g i s t e r 1 0 ( b c 1 0 ) b l o c k c o n t r o l r e g i s t e r 1 1 ( b c 1 1 ) b l o c k c o n t r o l r e g i s t e r 1 2 ( b c 1 2 ) port p7 (p7) s f r 1 a r e a ( a d d r e s s e s c 0 1 6 t o d f 1 6 ) : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : < b i t a l l o c a t i o n > < s t a t e i m m e d i a t e l y a f t e r r e s e t > f u n c t i o n b i t : no function bit : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 immediately after reset : indeterminate immediately after reset 0 1 ? : 1 immediately after reset 1 0 b l o c k c o n t r o l r e g i s t e r 1 3 ( b c 1 3 ) block control register 14 (bc 14 ) b l o c k c o n t r o l r e g i s t e r 1 5 ( b c 1 5 ) b l o c k c o n t r o l r e g i s t e r 1 6 ( b c 1 6 ) b 7b 0b7 b0 ? 0 0 1 6 ? 0 0 1 6 ? 00 16 ? ? ? ? ? ? ? ? ? ? r 0 g b out1 out2 0 0? 0 0? ? 0 ? ? ? ? ? ? ? oc16 oc17 oc14 oc15 oc12 oc13 oc10 oc11 0 0 1 6 bc 1 0 bc 1 1 bc 1 2 bc 1 3 bc 1 4 bc 1 5 bc 1 6 b c 2 0 b c 2 1 bc 2 2 b c 2 3 bc 2 4 b c 2 5 b c 2 6 b c 3 0 b c 3 1 bc 3 2 b c 3 3 bc 3 4 b c 3 5 b c 3 6 b c 4 0 b c 4 1 bc 4 2 b c 4 3 bc 4 4 b c 4 5 b c 4 6 b c 5 0 b c 5 1 bc 5 2 b c 5 3 bc 5 4 b c 5 5 b c 5 6 bc 6 0 bc 6 1 bc 6 2 bc 6 3 bc 6 4 bc 6 5 bc 6 6 bc 7 0 bc 7 1 bc 7 2 bc 7 3 bc 7 4 bc 7 5 bc 7 6 b c 8 0 b c 8 1 bc 8 2 b c 8 3 bc 8 4 b c 8 5 b c 8 6 b c 9 0 b c 9 1 bc 9 2 b c 9 3 bc 9 4 b c 9 5 b c 9 6 b c 1 0 0 b c 1 0 1 b c 1 0 2 b c 1 0 3 b c 1 0 4 b c 1 0 5 b c 1 0 6 b c 1 1 0 b c 1 1 1 b c 1 1 2 b c 1 1 3 b c 1 1 4 b c 1 1 5 b c 1 1 6 b c 1 2 0 b c 1 2 1 b c 1 2 2 b c 1 2 3 b c 1 2 4 b c 1 2 5 b c 1 2 6 hp6 hp7 hp4 hp5 hp2 hp3 hp0 hp1 00 16 0 0 00 16 ? 0 0 1 6 ? 0 0 1 6 ? t 3 c s b c 1 3 0 b c 1 3 1 b c 1 3 2 b c 1 3 3 b c 1 3 4 b c 1 3 5 b c 1 3 6 b c 1 4 0 b c 1 4 1 b c 1 4 2 b c 1 4 3 b c 1 4 4 b c 1 4 5 b c 1 4 6 b c 1 5 0 b c 1 5 1 b c 1 5 2 b c 1 5 3 b c 1 5 4 b c 1 5 5 b c 1 5 6 b c 1 6 0 b c 1 6 1 b c 1 6 2 b c 1 6 3 b c 1 6 4 b c 1 6 5 b c 1 6 6 p6im rgb 2bit m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 134 of 170 f 0 1 6 f 1 1 6 f 2 1 6 f 3 1 6 f 4 1 6 f 5 1 6 f 6 1 6 f 7 1 6 f 8 1 6 f 9 1 6 f a 1 6 f b 1 6 f c 1 6 f d 1 6 f e 1 6 f f 1 6 e 0 1 6 e 1 1 6 e 2 1 6 e 3 1 6 e 4 1 6 e 5 1 6 e 6 1 6 e7 16 e 8 1 6 e 9 1 6 e b 1 6 e c 1 6 e d 1 6 e e 1 6 e f 1 6 e a 1 6 d a t a s l i c e r c o n t r o l r e g i s t e r 1 ( d s c 1 ) a - d c o n v e r s i o n r e g i s t e r ( a d ) a - d c o n t r o l r e g i s t e r ( a d c o n ) t i m e r 1 ( t 1 ) c a p t i o n d a t a r e g i s t e r 1 ( c d 1 ) t i m e r 2 ( t 2 ) t i m e r 3 ( t 3 ) t i m e r 4 ( t 4 ) t i m e r m o d e r e g i s t e r 1 ( t m 1 ) t i m e r m o d e r e g i s t e r 2 ( t m 2 ) i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) i 2 c c o n t r o l r e g i s t e r ( s 1 d ) i 2 c clock control register (s2) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) interrupt request register 2 (ireq2) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) c p u m o d e r e g i s t e r ( c m ) d a t a s l i c e r c o n t r o l r e g i s t e r 2 ( d s c 2 ) i 2 c status register (s1) i 2 c address register (s0d) s f r 1 a r e a ( a d d r e s s e s e 0 1 6 t o f f 1 6 ) a d d r e s sr e g i s t e r b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t : fix to this bit to 0 (do not write to 1 ) : < b i t a l l o c a t i o n > < s t a t e i m m e d i a t e l y a f t e r r e s e t > f u n c t i o n b i t : no function bit : fix to this bit to 1 (do not write to 0 ) n a m e : : 0 immediately after reset : indeterminate immediately after reset 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 caption data register 2 (cd2) c a p t i o n d a t a r e g i s t e r 3 ( c d 3 ) c a p t i o n d a t a r e g i s t e r 4 ( c d 4 ) caption position register (cps) data slicer test register 2 data slicer test register 1 s ync s i gna l counter reg i ster (hc) cl oc k run- i n d etect reg i ster (crd) d a t a c l o c k p o s i t i o n r e g i s t e r ( d p s ) b7 b0 b7 b 0 t m 2 0 t m 2 1 t m 2 2 t m 2 3 tm24 t m 1 0 t m 1 1 t m 1 2 t m 1 3 tm14 cm2 t m 1 r t m 2 r t m 3 r t m 4 r osdr v s c r adr ck0 in1r dsr s i o r t m 1 e t m 2 e t m 3 e t m 4 e o s d e v s c e i n 1 e dse s i o e in2e t m 2 5 ff 16 0 7 1 6 ff 16 0 7 1 6 tm15 t m 1 6 t m 1 7 tm26 t m 2 7 ? s a d 0 s a d 1 s a d 2 sad3 s a d 4 s a d 5 sad6 rb w l r b ad0 aas al p i n bb t r x m s t bc0 bc1 bc2 eso als bsel 0 bsel 1 ccr0 ccr1 ccr2 ccr3 ccr4 ac k 0 0 1 6 00 16 0 0 1 6 ck r i n 2 r i i c r tm 56 r ade cke iice tm 56 e t m 5 6 s 0 0 cm7 cm5 cm6 adin0 adin1 adin2 a d v r e f a d s t r 1 0 b i t s a d 00 16 0 0 1 6 00 16 d s c 1 0 d s c 1 1 d s c 1 2 d s c 2 0 d s c 2 3 d s c 2 4 d s c 2 5 c r d 3 crd4 c r d 5 c r d 6 crd7 dps3 d p s 4 d p s 5 dps6 d p s 7 cps0 cps3 cps4 cps5 cps1 cps2 cps6 cps7 hc0 hc3 hc4 hc5 hc1 hc2 0? 0? 0 ? ?? 0 00 00 0 0 0 1 0 1 0 1 0 0 1 6 c d h 1 0 cdh13 cdh14 cdh15 cdh11 cdh12 c d h 1 6 c d h 1 7 cdl10 c d l 1 3 cdl14 cdl15 c d l 1 1 c d l 1 2 c d l 1 6 c d l 1 7 00 16 0 0 1 6 00 16 0 0 1 6 00 16 00 16 00 16 0 0 1 6 00 16 d1 d2 d3 d4 d5 d6 d7 d0 0 0 00?00 0 0 0 0 01 0 0? fast mode a c k b i t 0 c d h 2 0 cdh23 cdh24 cdh25 cdh21 cdh22 c d h 2 6 c d h 2 7 cdl20 cdl23 cdl24 cdl25 cdl21 cdl22 cdl26 cdl27 00 16 00 16 00 16 0 0 1 6 ? ? 0 0 0? 001 0 0 9 1 6 3 c 1 6 0 b a n k c o n t r o l r e g i s t e r ( b k ) bk0 b k 3 bk1 b k 2 b k 6 b k 7 00 ? ? 00??? ? rev.1.01 2003.07.16 page 135 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp : : < s t a t e i m m e d i a t e l y a f t e r r e s e t > : n a m e : : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 b 7b 0b 7b0 0 0 1 6 ? ? ? ? ? ? ? 0 0 1 6 0 0 1 6 0 0 1 6 p w 0 p w 1 p w 2 p w 3 p w 4 p w 5 p w 6 p n 3 r e 1 r e 2 r e 3 r e 5 i n t 3 p o l a d / i n t 3 s e l p o l 3 a d / i n t 3 s e l s m 0 r e 1 r e 2 r e 3 s m 4 r e 5 i n t 3 p o l a d / i n t 3 s e l s m 1 s m 2 s m 3 s m 5 p c 0 r e 1 r e 2 r e 3 p c 4 r e 5 i n t 3 p o l a d / i n t 3 s e l p c 1 p c 2 p c 5 p c 6 p c 7 r e 1 r e 2 a d / i n t 3 s e l c s 0 c s 1 c s 2 r e 1 r e 2 r e 3 r e 5 i n t 3 p o l a d / i n t 3 e l r e 1 r e 2 r e 3 t b 2 0 t b 2 1 b b 2 0 b b 2 1 ? ? ? 0 0 1 6 0 0 1 6 p n 0 0 o c 3 0 o c 3 1 o c 3 2 ? ? 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 7 1 6 ? ? b b 1 7 b b 1 6 b b 1 5b b 1 4 b b 1 3b b 1 2b b 1 1 b b 1 0 t b 1 7t b 1 6 t b 1 5t b 1 4 t b 1 3t b 1 2t b 1 1 t b 1 0 f f 1 6 o c 2 7 o c 2 5o c 2 4 o c 2 3o c 1 2o c 2 1 o c 2 0 o c 3 3 o c 3 4 r e 1 r e 2 r e 3 r e 5 a d / i n t 3 s e l 00 0 0 1 6 ? 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 00 o c 2 6 r c r 0 r c r 1 p n 4 p o l 2p o l 1 o c 3 5 o c 3 6 o c 3 7 s m 6 8 0 1 6 0 0 address register 200 16 pwm0 register (pwm0) 201 16 pwm1 register (pwm1) 202 16 pwm2 register (pwm2) 203 16 pwm3 register (pwm3) 204 16 pwm4 register (pwm4) 205 16 pwm5 register (pwm5) 205 16 pwm6 register (pwm6) 207 16 208 16 209 16 20a 16 20b 16 20c 16 20d 16 20e 16 20f 16 21a 16 21b 16 21c 16 21d 16 21e 16 21f 16 210 16 211 16 212 16 213 16 214 16 215 16 216 16 217 16 218 16 219 16 pwm7 register (pwm7) pwm mode register 1 (pn) pwm mode register 2 (pw) rom correction address 1 (high-order) rom correction address 1 (low-order) rom correction address 2 (high-order) rom correction address 2 (low-order) rom correction enable register (rcr) test register interrupt input polarity register (ip) serial i/o mode register (sm) serial i/o register (sio) osd control register 2(oc2) clock control register (cs) i/o polarity control register (pc) raster color register (rc) osd control register 3(oc3) timer 5 (tm5) timer 6 (tm6) top border control register 1 (tb1) bottom border control register 1 (bb1) top border control register 2 (tb2) bottom border control register 2 (bb2) sfr2 area (addresses 200 16 to 21f 16 ) < bit allocation > function bit no function bit fix to this bit to 0 (do not write to 1 ) fix to this bit to 1 (do not write to 0 ) bit allocation state immediately after reset rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 136 of 170 2 3 0 1 6 2 3 1 1 6 232 16 2 3 3 1 6 2 3 4 1 6 235 16 2 3 6 1 6 2 3 7 1 6 238 16 2 3 9 1 6 2 3 a 1 6 2 3 b 1 6 23c 16 23d 16 2 3 e 1 6 2 3 f 1 6 2 2 0 1 6 221 16 2 2 2 1 6 2 2 3 1 6 2 2 4 1 6 225 16 226 16 2 2 7 1 6 2 2 8 1 6 229 16 2 2 b 1 6 22c 16 2 2 d 1 6 2 2 e 1 6 22f 16 22a 16 vertical position register 1 11 (vp1 11 ) vertical position register 1 3 (vp1 3 ) vertical position register 1 7 (vp1 7 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 5 ( v p 1 5 ) vertical position register 1 6 (vp1 6 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 1 ( v p 1 1 ) vertical position register 1 2 (vp1 2 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 9 ( v p 1 9 ) vertical position register 1 10 (vp1 10 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 4 ( v p 1 4 ) vertical position register 1 12 (vp1 12 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 8 ( v p 1 8 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 3 ( v p 2 3 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 7 ( v p 2 7 ) vertical position register 2 5 (vp2 5 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 6 ( v p 2 6 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 1 ( v p 2 1 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 9 ( v p 2 9 ) vertical position register 2 10 (vp2 10 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 4 ( v p 2 4 ) vertical position register 2 12 (vp2 12 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 8 ( v p 2 8 ) vertical position register 2 2 (vp2 2 ) vertical position register 2 11 (vp2 11 ) s f r 2 a r e a ( a d d r e s s e s 2 2 0 1 6 t o 2 3 f 1 6 ) a d d r e s sr e g i s t e r bit allocation s t a t e i m m e d i a t e l y a f t e r r e s e t : fix to this bit to 0 (do not write to 1 ) : < bit allocation > < state immediately after reset > function bit : no function bit : fix to this bit to 1 (do not write to 0 ) n ame : : 0 immediately after reset : indeterminate immediately after reset 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 vertical position register 2 14 (vp2 14 ) vertical position register 2 13 (vp2 13 ) vertical position register 2 16 (vp2 16 ) vertical position register 2 15 (vp2 15 ) vertical position register 1 13 (vp1 13 ) vertical position register 1 14 (vp1 14 ) vertical position register 1 15 (vp1 15 ) vertical position register 1 16 (vp1 16 ) b 7b 0b 7b 0 ? ? ? ? v p 1 1 2 v p 1 1 3 v p 1 1 4 v p 1 1 5 v p 1 1 6 v p 1 1 7 v p 1 2 2 v p 1 2 3 v p 1 2 4 v p 1 2 5 v p 1 2 6 v p 1 2 7 v p 1 3 2 v p 1 3 3 v p 1 3 4 v p 1 3 5 v p 1 3 6 v p 1 3 7 v p 1 4 2 v p 1 4 3 v p 1 4 4 v p 1 4 5 v p 1 4 6 v p 1 4 7 v p 1 5 2 v p 1 5 3 v p 1 5 4 v p 1 5 5 v p 1 5 6 v p 1 5 7 v p 1 6 2 v p 1 6 3 v p 1 6 4 v p 1 6 5 v p 1 6 6 v p 1 6 7 v p 1 7 2 v p 1 7 3 v p 1 7 4 v p 1 7 5 v p 1 7 6 v p 1 7 7 v p 1 8 2 v p 1 8 3 v p 1 8 4 v p 1 8 5 v p 1 8 6 v p 1 8 7 v p 1 9 2 v p 1 9 3 v p 1 9 4 v p 1 9 5 v p 1 9 6 v p 1 9 7 v p 1 1 0 2 v p 1 1 0 3 v p 1 1 0 4 v p 1 1 0 5 v p 1 1 0 6 v p 1 1 0 7 v p 1 1 1 2 v p 1 1 1 3 v p 1 1 1 4 v p 1 1 1 5 v p 1 1 1 6 v p 1 1 1 7 v p 1 1 1 v p 1 2 1 v p 1 3 1 v p 1 4 1 v p 1 5 1 v p 1 6 1 v p 1 7 1 v p 1 8 1 v p 1 9 1 v p 1 1 0 1 v p 1 1 1 1 v p 1 1 2 1 v p 1 1 2 2 v p 1 1 2 3 v p 1 1 2 4 v p 1 1 2 5 v p 1 1 2 6 v p 1 1 2 7 v p 2 1 0 v p 2 1 1 v p 2 2 0 v p 2 2 1 v p 2 3 0 v p 2 3 1 v p 2 4 0 v p 2 4 1 v p 2 5 0 v p 2 5 1 v p 2 6 0 v p 2 6 1 v p 2 7 0 v p 2 7 1 v p 2 8 0 v p 2 8 1 v p 2 9 0 v p 2 9 1 v p 2 1 0 0 v p 2 1 0 1 v p 2 1 1 0 v p 2 1 1 1 v p 2 1 2 0 v p 2 1 2 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? v p 1 1 0 v p 1 2 0 v p 1 3 0 v p 1 4 0 v p 1 5 0 v p 1 6 0 v p 1 7 0 v p 1 8 0 v p 1 9 0 v p 1 1 0 0 v p 1 1 1 0 v p 1 1 2 0 v p 2 1 3 0 v p 2 1 3 1 v p 2 1 4 0 v p 2 1 4 1 v p 2 1 5 0 v p 2 1 5 1 v p 2 1 6 0 v p 2 1 6 1 v p 1 1 4 2 v p 1 1 4 3 v p 1 1 4 4 v p 1 1 4 5 v p 1 1 4 6 v p 1 1 4 7 v p 1 1 5 2 v p 1 1 5 3 v p 1 1 5 4 v p 1 1 5 5 v p 1 1 5 6 v p 1 1 5 7 v p 1 1 6 2 v p 1 1 6 3 v p 1 1 6 4 v p 1 1 6 5 v p 1 1 6 6 v p 1 1 6 7 v p 1 1 4 0 v p 1 1 5 0 v p 1 1 6 0 v p 1 1 4 1 v p 1 1 5 1 v p 1 1 6 1 v p 1 1 3 1 v p 1 1 3 2 v p 1 1 3 3 v p 1 1 3 4 v p 1 1 3 5 v p 1 1 3 6 v p 1 1 3 7v p 1 1 3 0 rev.1.01 2003.07.16 page 137 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp sfr2 area (addresses 240 16 to 258 16 ) 250 16 251 16 252 16 253 16 254 16 255 16 256 16 257 16 258 16 240 16 241 16 242 16 243 16 244 16 245 16 246 16 247 16 248 16 249 16 24b 16 24c 16 24d 16 24e 16 24f 16 24a 16 : fix to this bit to 0 (do not write to 1 ) : < bit allocation > < state immediately after reset > function bit : no function bit : fix to this bit to 1 (do not write to 0 ) name : : 0 immediately after reset : indeterminate immediately after reset 0 1 ? : 1 immediately after reset 1 0 address register bit allocation state immediately after reset color pallet register 1 (cr1) color pallet register 2 (cr2) color pallet register 3 (cr3) color pallet register 4 (cr4) color pallet register 5 (cr5) color pallet register 6 (cr6) color pallet register 7 (cr7) color pallet register 9 (cr9) color pallet register10 (cr10) color pallet register 11 (cr11) color pallet register 12 (cr12) color pallet register 13 (cr13) color pallet register 14 (cr14) color pallet register 15 (cr15) left border control register 1 (lb1) left border control register 2 (lb2) right border control register 1 (rb1) right border control register 2 (rb2) sprite vertical position register 1 (vs1) sprite vertical position register 2 (vs2) sprite osd control register (sc) sprite horizontal position register 1 (hs1) sprite horizontal position register 2 (hs2) b7 b0 b7 b0 ? ? ? cr 1 2 cr 1 3 cr 1 4 cr 1 5 cr 1 6 cr 2 2 cr 2 3 cr 2 4 cr 2 5 cr 2 6 cr 3 2 cr 3 3 cr 3 4 cr 3 5 cr 3 6 cr 4 2 cr 4 3 cr 4 4 cr 4 5 cr 4 6 cr 5 2 cr 5 3 cr 5 4 cr 5 5 cr 5 6 cr 6 2 cr 6 3 cr 6 4 cr 6 5 cr 6 6 cr 7 2 cr 7 3 cr 7 4 cr 7 5 cr 7 6 cr 9 2 cr 9 3 cr 9 4 cr 9 5 cr 9 6 cr 10 2 cr 10 3 cr 10 4 cr 10 5 cr 10 6 cr 11 2 cr 11 3 cr 11 4 cr 11 5 cr 11 6 cr 1 1 cr 2 1 cr 3 1 cr 4 1 cr 5 1 cr 6 1 cr 7 1 cr 9 1 cr 10 1 cr 11 1 cr 12 1 cr 12 2 cr 12 3 cr 12 4 cr 12 5 cr 12 6 lb10 lb11 vs10 vs11 vs20 vs21 hs10 hs11 hs20 hs21 sc0 sc1 ? ? ? ? ? ? ? ? ? ? ? ? 07 16 ff 16 ? 00 16 00 16 cr 1 0 cr 2 0 cr 3 0 cr 4 0 cr 5 0 cr 6 0 cr 7 0 cr 9 0 cr 10 0 cr 11 0 cr 12 0 cr 14 2 cr 14 3 cr 14 4 cr 14 5 cr 14 6 cr 15 2 cr 15 3 cr 15 4 cr 15 5 cr 15 6 cr 14 0 cr 15 0 cr 14 1 cr 15 1 cr 13 1 cr 13 2 cr 13 3 cr 13 4 cr 13 5 cr 13 6cr 13 0 lb12 lb13 lb14 lb15 lb16 lb17 lb20 lb21 lb22 rb10 rb11 rb12 rb13 rb14 rb15 rb16 rb17 rb20 rb21 rb22 vs12 vs13 vs14 vs15 vs16 vs17 hs12 hs13 hs14 hs15 hs16 hs17 hs22 sc2 sc3 sc4 sc5 ? 00 16 01 16 ? ? ? ? 0 0 0 0 0 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 138 of 170 internal state of processor status register and program counter at reset b 7 b 0 b 7 b 0 1 register p r o c e s s o r s t a t u s r e g i s t e r ( p s ) bit allocation state immediately after reset p r o g r a m c o u n t e r ( p c h ) p r o g r a m c o u n t e r ( p c l ) c o n t e n t s o f a d d r e s s f f f f 1 6 c o n t e n t s o f a d d r e s s f f f e 1 6 i zc d b t v n?? ? ? ? ? ? : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : < b i t a l l o c a t i o n > < s t a t e i m m e d i a t e l y a f t e r r e s e t > f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 rev.1.01 2003.07.16 page 139 of 170 m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows: ( n o t e 1 ) ( n o t e 2 ) 2: bit attributes the attributes of control register bits are classified into 3 types : read-only, write-only and read and write. in the figure, these attributes are represented as follows : : bit in which nothing is assigned n o t e s 1 : v a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e 0 0 a f t e r r e s e t r e l e a s e 1 1 a f t e r r e s e t r e l e a s e i n d e t e r m i n a t e i n d e t e r m i n a t e a f t e r r e s e t r e l e a s e r e a d e n a b l e d r e a d d i s a b l e d r r r e a d w r i t e e n a b l e d w r i t e d i s a b l e d 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . w w r i t e w ? b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b a f t e r r e s e t r w c p u m o d e r e g i s t e r 0 , 1 2 3 , 4 0 1 n a m e function s processor mode bits (cm0, cm1) 0 0 : s i n g l e - c h i p m o d e 0 1 : 1 0 : n o t a v a i l a b l e 1 1 : f i x t h e s e b i t s t o 1 . 0 stack page selection bit (see note) (cm2) 1 b 1 b 0 0: 0 page 1: 1 page 1 0 0 5 1 n o t h i n g i s a s s i g n e d . t h i s b i t i s w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . 6, 7 0 clock switch bits (cm6, cm7) 0 0: f(x in ) = 8 mhz 0 1: f(x in ) = 12 mhz 1 0: f(x in ) = 16 mhz 1 1: do not set b 7 b 6 cpu mode register (cpum) (cm) [address 00fb 16 ] r w r w r w r w r w < e x a m p l e > b i t s p o s i t i o nb i t a t t r i b u t e s v a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 140 of 170 addresses 00c1 16 , 00c3 16 , 00c5 16 address 00c7 16 b7 b6 b5 b4 b3 b2 b1 b0 port p3 direction register (d3) [address 00c7 16 ] b name functions after reset rw port p3 direction register 0 0 : port p3 0 input mode 1 : port p3 0 output mode 0 1 0 : port p3 1 input mode 1 : port p3 1 output mode 0 0 port p3 direction register nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. rw rw r 2 to 5 6 refer to timer section. timer 3 count source selection bit (t3cs) 0rw 7 refer to clock control register (address 0216 16 ). ports p6 3 , p6 4 selection bits (p6im) 0rw b7 b6 b5 b4 b3 b2 b1 b0 port pi direction register (di) (i=0,1,2) [addresses 00c1 16, 00c3 16 , 00c5 16 ] b name functions after reset r w port pi direction register 00 : port pi 0 input mode 1 : port pi 0 output mode 0 1 0 : port pi 1 input mode 1 : port pi 1 output mode 0 2 0 : port pi 2 input mode 1 : port pi 2 output mode 0 30 : port pi 3 input mode 1 : port pi 3 output mode 0 40 : port pi 4 input mode 1 : port pi 4 output mode 0 50 : port pi 5 input mode 1 : port pi 5 output mode 0 60 : port pi 6 input mode 1 : port pi 6 output mode 0 7 0 : port pi 7 input mode 1 : port pi 7 output mode 0 port pi direction register rw rw rw rw rw rw rw rw rev.1.01 2003.07.16 page 141 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp address 00c9 16 address 00cb 16 b7 b6 b5 b4 b3 b2 b1 b0 osd port control register (pf) [address 00cb 16 ] b name functions after reset r w osd port control register 00 r w fix this bit to 0 00 2 0 : r signal output 1 : port p5 2 output 0 r w 3 port p5 3 output signal selection bit (g) 0 : g signal output 1 : port p5 3 output 0 r w 4 port p5 4 output signal selection bit (b) 0 : b signal output 1 : port p5 4 output 0 r w 5 port p5 5 output signal selection bit (out1) 0 : out1 signal output 1 : port p5 5 output 0 r w 6 port p1 0 output signal selection bit (out2) 0 : port p1 0 signal output 1 : out2 output 0 r w port p5 2 output signal selection bit (r) 70 r w fix this bit to 0 1 0 : 4-adjustment-level analog is output from pins r, g, b. 1 : value which is converted from 4-adjustment-level analog to 2-bit digital is output as below: high-order: from r1, g1, b1 low-order: from r0, g0, b0 0 r w r, g, b output method selection bit (rgb2bit) b7 b6 b5 b4 b3 b2 b1 b0 b name functions after reset r w port p4 direction register 00 1 to 4 0 0 fix this bit to 0 rw r w r 5 6 port p4 direction register 0 r w 7 0 r nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. nothing is assigned. this bit is write disable bit. when this bit is read out, the values is 0. port p3 direction register (d4) [address 00c9 16 ] 0 ? when serial i/o is used 0 : port p4 5 input mode 1 : s out output ? 0 : port p4 6 input mode 1 : s out output ? m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 142 of 170 address 00ce 16 0 : color signal of character background part does not flash 1 : color signal of character background part flashes b7 b6 b5 b4 b3 b2 b1 b0 osd control register 1 (oc1) [address 00ce 16 ] b name functions after reset r w osd control register 1 0 osd control bit (oc10) (see note 1) 0 : all-blocks display off 1 : all-blocks display on 0 1 scan mode selection bit ( oc11 ) 0 : normal scan mode 1 : bi-scan mode 0 2 0 : all bordered 1 : shadow bordered (see note 2) 0 0 4 automatic solid space control bit (oc14) 0 border type selection bit ( oc12 ) rw rw rw r w rw 3 flash mode selection bit ( oc13 ) 6, 7 0 0: logic sum (or) of layer 1 s color and layer 2 s color 0 1: layer 1 s color has priority 1 0: layer 2 s color has priority 1 1: do not set. layer mixing control bits (oc16, oc17) ( see note 3 ) b7 b6 0 : off 1 : on 0rw 5 vertical window/blank control bit (oc15) 0rw 0 : off 1 : on notes 1 : even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next v sync . 2: shadow border is output at right and bottom side of the font. 3: out2 is always ored, regardless of values of these bits. address 00cf 16 b7 b6 b5 b4 b3 b2 b1 b0 horizontal position register (hp) [address 00cf 16 ] b name functions after reset rw horizontal position register control bits of horizontal display start positions (hp0 to hp7) horizontal display start positions 4t osc ? (setting value of high-order 4 bits ? 16 1 +setting value of low-order 4 bits ? 16 0 ) 0rw 0 to 7 notes 1. the setting value synchronizes with the v sync . 2. t osc = osd oscillation period. rev.1.01 2003.07.16 page 143 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp addresses 00d0 16 to 00df 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1b 0 block control register i (bci) (i=1 to 16) [addresses 00d0 16 to 00df 16 ] b l o c k c o n t r o l r e g i s t e r i 0 , 1 display mode selection bits (bci0, bci1) i n d e t e r m i n a t e 3 , 4 d o t s i z e s e l e c t i o n b i t s ( b c i 3 , b c i 4 ) 5, 6 pre-divide ratio selection bit (bci5, bci6) 7 b1 b0 0 0: display off 0 1: osd mode 1 0: cc mode 1 1: cdosd mode b n a m e function s a f t e r r e s e tr w r w i n d e t e r m i n a t e r w i n d e t e r m i n a t e r w i n d e t e r m i n a t e r notes 1: tc is osd clock cycle divided in pre-divide circuit. 2: h is h sync. 3: this character size is available only in layer 2. at this time, set layer 1 s pre-divide ratio = ? 2, layer 1 s horizontal dot size = 1tc. b 6 b 5 b 4 b 3 p r e - d i v i d e d o t s i z e r a t i o 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 1 1 ? 1 ? 2 ? 3 1tc ? 1/2h 1tc ? 1h 2tc ? 2h 3tc ? 3h 1tc ? 1/2h 1tc ? 1h 2tc ? 2h 3tc ? 3h 1.5tc ? 1/2h (see note 3) 1.5tc ? 1h (see note 3) 1tc ? 1/2h 1tc ? 1h 2tc ? 2h 3tc ? 3h 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is indeterminate. 2b o r d e r c o n t r o l b i t ( b c i 2 ) 0 : b o r d e r o f f 1 : b o r d e r o n i n d e t e r m i n a t e r w m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 144 of 170 address 00e0 16 b7 b6 b5 b4 b3 b2 b1 b0 data slicer control register 1(dsc1) [address 00e0 16 ] data slicer control register 1 00 rw 0rw 2 reference clock source selection bit (dsc12) 0: video signal 1: h sync signal 0r w 0rw 00 0: stopped 1: operating data slicer and timing signal generating circuit control bit (dsc10) fix these bits to 0. 3 to 7 000 10: f2 1: f1 selection bit of data slice reference voltage generating field (dsc11) definition of fields 1 (f1) and 2 (f2) h sep v sep f1: h sep v sep f2: b after reset r w name functions address 00e1 16 b7 b6 b5 b4 b3 b2 b1 b0 data slicer control register 2 (dsc2) [address 00e1 16 ] data slicer control register 2 0 indeterminate 0 indeterminate indeterminate 00 0: data is not latched yet and a clock-run-in is not determined. 1: data is latched and a clock-run-in is determined. caption data latch completion flag 1 (dsc20) fix this bit to 0. read-only test bit 30: f2 1: f1 field determination flag(dsc23) 4 0: method (1) 1: method (2) vertical synchronous signal (v sep ) generating method selection bit (dsc24) 0 5 0: match 1: mismatch v-pulse shape determination flag (dsc25) indeterminate b after reset function s nam e definition of fields 1 (f1) and 2 (f2) h sep v sep f1: h sep v sep f2: 0 indeterminate r w r r w r ? r ? r w r ? r w r ? fix this bit to 0. read-only test bit 6 7 1 2 rev.1.01 2003.07.16 page 145 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp address 00ea 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c l o c k r u n - i n d e t e c t r e g i s t e r ( c r d ) [ a d d r e s s 0 0 e a 1 6 ] r w c l o c k r u n - i n d e t e c t r e g i s t e r 0 t o 2 0 r t est bi ts 3 t o 7 n u m b e r o f r e f e r e n c e c l o c k s t o b e c o u n t e d i n o n e c l o c k r u n - i n p u l s e p e r i o d . cl oc k run- i n d etect i on bit(crd3 to crd7) 0 r r e a d - o n l y b a f t e r r e s e t f unct i on s n a m e address 00e6 16 address 00e9 16 b7 b6 b5 b4 b3 b2 b1 b0 caption position register (cps) [address 00e6 16 ] caption position registe r 0 to 4 0 r w 0 r w caption position bits(cps0 to cps4) 6, 7 refer to the corresponding table (table 8.10.1). slice line mode specification bits (in 1 field) (cps6, cps7) 5 0: data is not latched yet and a clock-run-in is not determined. 1: data is latched and a clock-run-in is determined. caption data latch completion flag 2 (cps5) indeterminate r b after reset functions nam e r w b7 b6 b5 b4 b3 b2 b1 b0 sync pulse counter register (hc) [address 00e9 16 ] r w sync pulse counter registe r 0 to 4 indeterminate r 6, 7 0 r count value (hc0 to hc4) 5 0 r w count source (hc5) 0: h sync signal 1: composite sync signal b after reset functions nam e nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 146 of 170 address 00ed 16 address 00eb 16 b7 b6 b5 b4 b3 b2 b1 b0 data clock position register (dps) [address 00eb 16 ] data clock position register 01 r w 3 data clock position set bits (dps3 to dps7) 1 r w fix these bits to 1. 1,2 fix this bit to 0. 0 r w 01 0 b function s name r w 4 to 7 0 after reset b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b a n k c o n t r o l r e g i s t e r ( b k ) [ a d d r e s s 0 0 e d 1 6 ] b n a m e f unct i ons b a n k c o n t r o l r e g i s t e r 0 t o 3 6, 7 b an k contro l bits (bk6, bk7) b an k num b er i s se l ecte d (b an k 11 to 15 ) b an k selection bits (bk0 to bk3) 4 , 5 f i x t h e s e b i t s t o 0 . a f t e r r e s e t r w 0 r w 0 r w 0 r w 0 ? 10 11 n ot use d u se d u se d r e a d o u t f r o m e x t r a a r e a ( p r o g r a m m a b l e ) r e a d o u t t h e d a t a f r o m a r e a s p e c i f i e d b y t h e b a n k s e l e c t i o n b i t s r e a d o u t f r o m e x t r a a r e a ( d a t a - d e d i c a t e d ) b 6 b an k rom a d d r e s s 1 0 0 0 1 6 l e v e l a c c e s s b 7 0 0 rev.1.01 2003.07.16 page 147 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp address 00ef 16 a-d control register b7 b6 b5 b4 b3 b2 b1 b0 a-d control register (adcon) [address 00ef 16 ] b after reset rw 0 to 2 analog input pin selection bits (adin0 to adin2) name functions b2 b1 b0 0 0 0 : ad1 0 0 1 : ad2 0 1 0 : ad3 0 1 1 : ad4 1 0 0 : ad5 1 0 1 : ad6 1 1 0 : ad7 1 1 1 : ad8 4 v cc connection selection bit (advref) 0: off 1: on 0 0 6 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is indeterminate. rw rw r 3 a-d conversion completion bit (adstr) 0: conversion in progress 1: convertion completed 1 rw 7 fix this bit to 0. rw 00 indeterminate 5 fix this bit to 0. rw 0 0 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 148 of 170 address 00f4 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 timer mode register 1 (tm1) [address 00f4 16 ] b after reset w t i m e r m o d e r e g i s t e r 1 0 1 2 3 4 n a m e functions t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t 1 ( t m 1 0 ) 0: f(x in )/16 or f(x cin )/16 (see note) 1: count source selected by bit 5 of tm1 t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t 1 ( t m 1 1 ) 0: count source selected by bit 4 of tm1 1: external clock from tim2 pin t i m e r 1 c o u n t s t o p b i t ( t m 1 2 ) 0: count start 1: count stop timer 2 count stop bit (tm13) 0: count start 1: count stop t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t 2 ( t m 1 4 ) r 0 0 0 0 0 w r w r w r w r w r 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 1 overflow 5 timer 1 count source selection bit 2 (tm15) 0: f(x in )/4096 or f(x cin )/4096 (see note) 1: external clock from tim2 pin 0w r 6 t i m e r 5 c o u n t s o u r c e s e l e c t i o n b i t 2 ( t m 1 6 ) 0: timer 2 overflow 1: timer 4 overflow 0w r 7 t i m e r 6 c o u n t s o u r c e s e l e c t i o n b i t ( t m 1 7 ) 0w r 0: f(x in )/16 or f(x cin )/16 (see note) 1: timer 5 overflow n o t e : e i t h e r f ( x i n ) o r f ( x c i n ) i s s e l e c t e d b y b i t 7 o f t h e c p u m o d e r e g i s t e r . rev.1.01 2003.07.16 page 149 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp address 00f5 16 b7 b6 b5 b4 b3 b2 b1 b0 timer mode register 2 (tm2) [address 00f5 16 ] b after reset r w timer mode register 2 0 name functions timer 3 count source selection bit (tm20) 0 rw 1, 4 timer 4 count source selection bits (tm21, tm24) 0 rw 2 3 0 timer 3 count stop bit (tm22) 0: count start 1: count stop timer 4 count stop bit (tm23) 0: count start 1: count stop 0 0 5 timer 5 count stop bit (tm25) 0: count start 1: count stop 0 6 timer 6 count stop bit (tm26) 0: count start 1: count stop 0 rw rw rw rw r w 7 timer 5 count source selection bit 1 (tm27) 0: f(x in )/16 or f(x cin )/16 (see note) 1: count source selected by bit 6 of tm1 b0 0 0 : f(x in )/16 or f(x cin )/16 (see note) 1 0 : f(x cin ) 01: 11 : (b6 at address 00c7 16 ) external clock from tim3 pin b4 b1 0 0 : timer 3 overflow signal 0 1 : f(x in )/16 or f(x cin )/16 (see note) 1 0 : f(x in )/2 or f(x cin )/2 (see note) 1 1 : f(x cin ) note: either f(x in ) or f(x cin ) is selected by bit 7 of the cpu mode register. m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 150 of 170 address 00f6 16 b7 b6 b5 b4 b3 b2 b1 b0 i 2 c data shift register (s0) [address 00f6 16 ] b functions after reset r w i 2 c data shift register 0 to 7 this is an 8-bit shift register to store receive data and write transmit data. indeterminate note: to write data into the i 2 c data shift register after setting the mst bit to 0 (slave mode), keep an interval of 8 machine cycles or more. name d0 to d7 rw address 00f7 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 r e a d / w r i t e b i t ( r b w ) 1 t o 7 sl ave a dd ress (sad0 to sad6) < o n l y i n 1 0 - b i t a d d r e s s i n g ( i n s l a v e ) m o d e > t h e l a s t s i g n i f i c a n t b i t o f a d d r e s s d a t a i s c o m p a r e d . 0 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r s t a r t c o n d i t i o n ( r e a d s t a t e ) 1 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r r e s t a r t c o n d i t i o n ( w r i t e s t a t e ) < i n b ot h mo d es> the address data is compared. i 2 c a d d r e s s r e g i s t e r i 2 c a d d r e s s r e g i s t e r ( s 0 d ) [ a d d r e s s 0 0 f 7 1 6 ] b n a m e function s 0 0 a f t e r r e s e t r w r r w rev.1.01 2003.07.16 page 151 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp address 00f8 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i 2 c status register (s1) [address 00f8 16 ] i 2 c s t a t u s r e g i s t e r 0 3 4 5 6, 7 b 7 b 6 0 0 : slave recieve mode 0 1 : slave transmit mode 1 0 : master recieve mode 1 1 : master transmit mode 1 2 0 0 0 1 0 b nam e function s a f t e r r e s e t r w c o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s ( t r x , m s t ) 0 : b us f ree 1 : bus busy b u s b u s y f l a g ( b b ) 0 : i nterrupt request i ssue d 1 : no interrupt request issued i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( p i n ) 0 : n ot d etecte d 1 : detected a r b i t r a t i o n l o s t d e t e c t i n g f l a g ( a l ) ( s e e n o t e ) 0 : add ress m i smatc h 1 : address match s l a v e a d d r e s s c o m p a r i s o n f l a g ( a a s ) ( s e e n o t e ) 0 : n o genera l ca ll d etecte d 1 : general call detected g e n e r a l c a l l d e t e c t i n g f l a g ( a d 0 ) ( s e e n o t e ) 0 : l ast bi t = 0 1 : last bit = 1 l a s t r e c e i v e b i t ( l r b ) ( s e e n o t e ) n o t e : t h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . i n d e t e r m i n a t e r r r r rw r w 0 r w ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) address 00f9 16 b7 b6 b5 b4 b3 b2 b1 b0 0 to 2 bit counter (number of transmit/recieve bits) (bc0 to bc2) b2 b1 b0 0 0 0: 8 0 0 1: 7 0 1 0: 6 0 1 1: 5 1 0 0: 4 1 0 1: 3 1 1 0: 2 1 1 1: 1 3i 2 c-bus interface use enable bit (eso) 0: disabled 1: enabled 4 data format selection bit (als) 0: addressing format 1: free data format 5 addressing format selection bit (10bit sad) 0: 7-bit addressing format 1: 10-bit addressing format 6, 7 connection control bits between i 2 c-bus interface and ports (bsel0, bsel1) b7 b6 connection port (see note) 0 0: none 0 1: scl1, sda1 1 0: scl2, sda2 1 1: scl1, sda1, scl2, sda2 0 0 0 0 0 i 2 c control register (s1d) [address 00f9 16 ] i 2 c control register b name function s after reset r w r w r w r w r w r w m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 152 of 170 address 00fa 16 b7 b6 b5 b4 b3 b2 b1 b0 i 2 c clock control register (s2) [address 00fa 16 ] i 2 c clock control register 0 to 4 scl frequency control bits (ccr0 to ccr4) 7 5 6 scl mode specification bit (fast mode) 0: standard clock mode 1: high-speed clock mode 0 standard clock mode b name function s after reset r w 0 0 0 ack bit (ack bit) ack clock bit (ack) 0: ack is returned. 1: ack is not returned. 0: no ack clock 1: ack clock high speed clock mode setup disabled setup disabled 00 to 02 333 03 250 04 100 400 (see note) 05 83.3 166 06 500/ccr value 1000/ccr value ... 17.2 34.5 1d 16.6 33.3 1e 16.1 32.3 1f note: at 400 khz in the high-speed clock mode, the duty is as below . 0 period : 1 period = 3 : 2 in the other cases, the duty is as below. 0 period : 1 period = 1 : 1 register value b4 to b0 r w r w r w r w (at f = 4 mhz, unit : khz) setup disabled setup disabled address 00fb 16 c p u m o d e r e g i s t e r b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b a f t e r r e s e tr w 0 , 1 2 3 , 4 0 1 n a m e f u n c t i o n s p r o c e s s o r m o d e b i t s ( c m 0 , c m 1 ) 0 0 : s i n g l e - c h i p m o d e 0 1 : 1 0 : n o t a v a i l a b l e 1 1 : f i x t h e s e b i t s t o 1 . 1 s t a c k p a g e s e l e c t i o n b i t ( c m 2 ) ( s e e n o t e ) 1 b 1 b 0 0 : 0 p a g e 1 : 1 p a g e 1 0 0 5 1 6 0 m a i n c l o c k ( x i n x o u t ) s t o p b i t ( c m 6 ) c p u m o d e r e g i s t e r ( c m ) [ a d d r e s s 0 0 f b 1 6 ] r w r w r w r w r w 0 : l o w d r i v e 1 : h i g h d r i v e 0 : o s c i l l a t i n g 1 : s t o p p e d 7 0 i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t ( c m 7 ) r w 0 : x i n x o u t s e l e c t e d ( h i g h - s p e e d m o d e ) 1 : x c i n x c o u t s e l e c t e d ( l o w - s p e e d m o d e ) n o t e : t h i s b i t i s s e t t o 1 a f t e r t h e r e s e t r e l e a s e . x c o u t d r i v a b i l i t y s e l e c t i o n b i t ( c m 5 ) rev.1.01 2003.07.16 page 153 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp address 00fc 16 address 00fd 16 b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 1 (ireq1) [address 00fc b name interrupt request register 1 0 timer 1 interrupt re q uest bit ( tm1r ) 1 timer 2 interrupt re q uest bit ( tm2r ) 2 timer 3 interrupt re q uest bit ( tm3r ) 3 timer 4 interrupt re q uest bit ( tm4r ) 4 osd interrupt request bit ( osdr ) 5v sync interrupt re q uest bit ( vscr ) 6 a-d conversion int3 external interrupt request bit ( adr ) 7 ? : 0 can be set by software, but 1 cannot be set. 16 ] functions 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued after reset rw 0 0 ? 0 ? 0 ? ? 0 ? 0 ? 0 ? r r r r r r r r nothing is assigned. this bit is a write disable bit. when this bit is read out , the value is 0. 0 b7 b 6 b5 b4 b3 b2 b1 b0 interrupt request register 2 (ireq2) [address 00fd b name interrupt request register 2 0 int1 external interrupt re q uest bit ( in1r ) 1 data slicer interrupt re q uest bit ( dsr ) 2 serial i/o interrupt re q uest bit ( sior ) 3 4 int2 external interrupt request bit ( in2r ) 5 7 fix this bit to 0. 0 ? : 0 can be set by software, but 1 cannot be set. 16 ] f(x in )/4096 sprite osd interru p t re q uest bit ( ckr ) multi-master i 2 c-bus interrupt re q uest bit ( iicr ) 6 timer 5 6 interrupt request bit (tm56r) functions 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued after reset 0 0 0 0 0 0 0 0 rw ? ? ? ? r r r r ? ? ? r m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 154 of 170 address 00fe 16 address 00ff 16 b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 1 (icon1) [address 00fe 16 ] b 0 na me interrupt control register 1 timer 1 interrupt enable bit (tm1e) 1 timer 2 interrupt enable bit (tm2e) 2 timer 3 interrupt enable bit (tm3e) 3 4 osd interrupt enable bit (osde) 7 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. timer 4 interrupt enable bit (tm4e) 5v sync interrupt enable bit (vsce) 6 a-d conversion int3 external interrupt enable bit (ade) functions 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enable d after reset 0 0 0 0 0 0 0 0 rw rw rw rw rw rw r rw rw b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 2 (icon2) [address 00ff 16 ] b name functions after reset interrupt control register 2 0 int1 external interrupt enable bit ( in1e ) 0 : interrupt disabled 1 : interrupt enabled 1 data slicer interrupt enable bit ( dse ) 2 serial i/o interrupt enable bit ( sioe ) 3 4 int2 external interrupt enable bit ( in2e ) 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 0 0 0 0 f(x in )/4096 sprite osd interrupt enable bit (cke) 0 : interrupt disabled 1 : interrupt enabled 5 multi-master i 2 c-bus interface interrupt enable bit (iice) 0 : interrupt disabled 1 : interrupt enabled 0 6 timer 5 6 interrupt enable bit ( tm56e ) 0 : interrupt disabled 1 : interrupt enabled 0 7 timer 5 6 interrupt switch bit ( tm56s ) 0 : timer 5 1 : timer 6 0 rw rw rw rw rw rw rw rw rw rev.1.01 2003.07.16 page 155 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp address 020a 16 address 020b 16 b 7 b 6 b 5 b 4 b 3 b 2 b1 b 0 pwm mode register 1 (pn) [address 020a 16 ] b after reset r w pwm mode re g ister 1 0 1, 2 0 nam e function s nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. r r pwm counts source selection bit (pn0) 0 : count source supply 1 : count source stop 3 pwm output polarity selection bit (pn3) 0 0 : positive polarity 1 : negative polarity r w 4 p0 3 /pwm7 output selection bit (pn4) 0 0 : p0 3 output 1 : pwm7 output r w 0 w 5 to 7 nothing is assigned. these bits are write disable bits. wh e n t h ese b i ts a r e r ead out, t h e v a l ues a r e 0 . r 0 b7 b6 b5 b4 b3 b2 b1 b0 pwm mode register 2 (pw) [address 020b 16 ] b after reset rw pwm mode register 2 0 1 2 3 4 0 name functions p0 4 /pwm0 output selection bit (pw0) 0 : p0 4 output 1 : pwm0 output p0 6 /pwm2 output selection bit (pw2) 0 : p0 6 output 1 : pwm2 output p0 7 /pwm3 output selection bit (pw3) 0 : p0 7 output 1 : pwm3 output p0 0 /pwm4 output selection bit (pw4) 0 : p0 0 output 1 : pwm4 output 5 p0 1 /pwm5 output selection bit (pw5) 0: p0 1 output 1: pwm5 output 7 p0 5 /pwm1 output selection bit (pw1) 0 : p0 5 output 1 : pwm1 output 0 0 0 0 0 0 rw rw rw rw rw rw rw 6 p0 2 /pwm6 output selection bit (pw6) 0: p0 2 output 1: pwm6 output 0 rw fix this bit to 0. 0 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 156 of 170 address 0210 16 address 0212 16 b7 b6 b5 b4 b3 b2 b1 b0 rom correction enable register (rcr) [address 0210 16 ] b after reset rw rom correction enable register 0 vector 1 enable bit (rcr0) name functions 0: disabled 1: enabled 1 vector 2 enable bit (rcr1) 0: disabled 1: enabled 4 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 0 0 rw rw r 0 0 2, 3 fix these bits to 0. 0 rw b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( i p ) [ a d d r e s s 0 2 1 2 1 6 ] b n am e f unct i on s a f t e r r e s e t r w i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r 0 0 t o 2 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . r ? i n t 1 p o l a r i t y s w i t c h b i t ( p o l 1 ) 0 0 3 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 4 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 6 i n t 2 p o l a r i t y s w i t c h b i t ( p o l 2 ) i n t 3 p o l a r i t y s w i t c h b i t ( p o l 3 ) r w r w r w 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 0 : i n t 3 i n t e r r u p t 1 : a - d c o n v e r s i o n i n t e r r u p t 7 a - d c o n v e r s i o n i n t 3 i n t e r r u p t s o u r c e s e l e c t i o n b i t ( a d / i n t 3 s e l ) r w 0 5 n o t h i n g i s a s s i g n e d . t h i s b i t i s w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . r ? 0 rev.1.01 2003.07.16 page 157 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp address 0213 16 b 7 b 6 b 5 b 4 b3 b 2 b1 b 0 s e r i a l i / o m o d e r e g i s t e r ( s m ) [ a d d r e s s 0 2 1 3 1 6 ] bn a m ef u n c t i o n s after reset rw s e r i a l i / o m o d e r e g i s t e r 0 , 1i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s ( s m 0 , s m 1 ) b1 b0 0 0: f(x in )/8 or f(x cin )/8 0 1: f(x in )/16 or f(x cin )/16 1 0: f(x in )/32 or f(x cin )/32 1 1: f(x in )/64 or f(x cin )/64 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s m 2 ) 3 p o r t f u n c t i o n s e l e c t i o n b i t ( s m 3 ) 6 5 transfer direction selection bit (sm5) 0 : p 1 1 , p 1 3 1 : s c l 1 , s d a 1 0: external clock 1: internal clock 0 : t r a n s f e r f r o m t h e l a s t s i g n i f i c a n t b i t ( l s b ) 1 : t r a n s f e r f r o m t h e t o p s i g n i f i c a n t b i t ( m s b ) 0 0 0 0 0 0 rw rw rw r w rw rw 4 p o r t f u n c t i o n s e l e c t i o n b i t ( s m 4 ) 0 : p 1 2 , p 1 4 1 : s c l 2 , s d a 2 7 n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . 0r s i n p i n s w i t c h b i t ( s m 6 ) 0: p1 7 is s in pin 1: p7 2 is s in pin m37281mah?xxsp,m37281mfh?xxsp,m37281mkh?xxsp, m37281eksp rev.1.01 2003.07.16 page 158 of 170 address 0215 16 b7 b6 b5 b4 b3 b2 b1 b0 osd control register 2 (oc2) [address 0215 16 ] b name functions osd control register 2 0, 1 2 r, g, b signal output selection bit(oc22) 3 5 window/blank selection bit 1 (horizontal) (oc25) solid space output bit (oc23) 0: out1 output 1: out2 output 0: digital output 1: analog output (4 gradations) 4 horizotal window/blank coutrol bit (oc24) 0: off 1: on b1 b0 layer 1 layer 2 0 0 cc, osd, cdosd 0 1 cc, osd cdosd 1 0 cc, cdosd osd 1 1 cc cdosd osd 0: horizontal blank function 1: horizontal window function 6 window/blank selection bit 2 (vertical) (oc26) 0: vertical blank function 1: vertical window function 7 osd interrupt request selection bit (oc27) r w 0 r w 0 r w 0 r w 0 r w 0 r w 0 r w 0 r w 0: at completion of layer 1 block display 1: at completion of layer 2 block display display layer selection bits (oc20, oc21) note: when setting bit 1 of the osd port control register to 1, the value which is converted from the 4-adjustment-level analog to the 2-bit digital is output regardless of this bit value as follows : the high-order bit (r1, g1 and b1) is output from pins p5 2 , p5 3 and p5 4 , and the low-order bit is (r0, g0 and b0) output from pins p1 7 , p1 5 and p1 6 . and besides, when not using osd function, the low-power dissipation can realize by setting this bit to 0. (see note) after reset rev.1.01 2003.07.16 page 159 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp address 0216 16 address 0217 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c l o c k c o n t r o l r e g i s t e r ( c s ) [ a d d r e s s 0 2 1 6 1 6 ] b n ame f u n c t i o n s a f t e r r e s e t r w c l o c k c o n t r o l r e g i s t e r 0 c l o c k s e l e c t i o n b i t ( c s 0 ) 0 r w 1, 2 0 : d a t a s l i c e r c l o c k 1 : o s c 1 c l o c k 0 r w 70 r w t est bi t (see note 2) osc 1 osc ill at i ng mo d e selection bits (cs1, cs2) 00 : 3 2 k h z o s c i l l a t i n g m o d e . 01 : u s e d a s i n p u t p o r t o f p 6 3 a n d p 6 4 ( s e e n o t e 1 ) . 10 : l c o s c i l l a t i n g m o d e 11 : c e r a m i c q u a r t z - c r y s t a l o s c i l l a t i n g m o d e b2 b1 n o t e 1 : s e t b i t 7 o f a d d r e s s 0 0 c 7 1 6 t o 1 , w h e n o s c 1 a n d o s c 2 a r e u s e d a s p 6 3 a n d p 6 4 . 2 : b e s u r e t o s e t b i t 7 t o 0 f o r p r o g r a m o f t h e m a s k a n d t h e e p r o m v e r s i o n s . f o r t h e e m u l a t o r m c u v e r s i o n ( m 3 7 2 8 0 e r s s ) , b e s u r e t o s e t b i t 7 t o 1 w h e n u s i n g t h e d a t a s l i c e r c l o c k f o r s o f t w a r e d e b u g g i n g . 00 0 f i x t h e s e b i t s t o 0 . 0 r w 3 to 6 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i / o p o l a r i t y c o n t r o l r e g i s t e r ( p c ) [ a d d r e s s 0 2 1 7 1 6 ] b n a m e f unct i on s a f t e r r e s e t r w i / o p o l a r i t y c o n t r o l r e g i s t e r 0 h sync i nput po l ar i ty switch bit (pc0) 0 : p os i t i ve po l ar i ty i nput 1 : negative polarity input 0 10 : p os i t i ve po l ar i ty i nput 1 : negative polarity input 0 2 r , g , b o u t p u t p o l a r i t y s w i t c h b i t ( p c 2 ) 0 : p os i t i ve po l ar i ty output 1 : negative polarity output 0 3 0 v s y n c i n p u t p o l a r i t y s w i t c h b i t ( p c 1 ) r w r w r w r n o t e : r e f e r t o f i g . 8 . 1 1 . 1 9 . 0 : at even fi e ld at odd field 1 : at even field at odd field 4 o u t 1 o u t p u t p o l a r i t y s w i t c h b i t ( p c 4 ) 0 : p os i t i ve po l ar i ty output 1 : negative polarity output 0 5 o u t 2 o u t p u t p o l a r i t y s w i t c h b i t ( p c 5 ) 0 : p os i t i ve po l ar i ty output 1 : negative polarity output 0 6 d i s p l a y d o t l i n e s e l e c t i o n b i t ( p c 6 ) ( s e e n o t e ) 0 7 f i e l d d e t e r m i n a t i o n f l a g ( p c 7 ) 0 : e ven fi e ld 1 : odd field 1 r w r w r w r n ot hi ng i s ass i gne d . thi s bi t i s a wr i te di sa bl e bi t. when this bit is read out, the value is 0 . m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 160 of 170 address 0218 16 address 0219 16 b7 b6 b5 b4 b3 b2 b1 b0 raster color register (rc) [address 0218 16 ] b name functions at reset r w raster color register 0, 1 raster color r control bits (rc0, rc1) 0 r w 2, 3 0 r w 4, 5 0 r w 0 0 w 6 70 r w r raster color g control bits (rc2, rc3) 0 0: no output (see note) 0 1: 1/3 v cc 1 0: 2/3 v cc 1 1: v cc b0 b1 note: when selecting digital output, v cc is output at any other values except 00. raster color b control bits (rc4, rc5) raster color out1 control bits (rc6) 0: no output 1: output 0 0: no output (see note) 0 1: 1/3 v cc 1 0: 2/3 v cc 1 1: v cc b3 b2 0 0: no output (see note) 0 1: 1/3 v cc 1 0: 2/3 v cc 1 1: v cc b5 b4 raster color out2 control bits (rc7) 0: no output 1: output b7 b6 b5 b4 b3 b2 b1 b0 osd control register 3 (oc3) [address 0219 16 ] b name functions r w osd control register 3 0 cc mode character color selection bit (oc30) 0 r w 1, 2 0: color code 0 to 7 1: color code 8 to 15 0 r w 30 r w 0 w 4 r cc mode character background color selection bits (oc31, oc32) (see note) 0 0: color code 0 to 3 0 1: color code 4 to 7 1 0: color code 8 to 11 1 1: color code 12 to 15 b1 b1 note: color pallet 8 is always selected for solid space (when out1 output is selected), regardress of value of this register. cdosd mode character color selection bit (oc33) 0: color code 0 to 7 1: color code 8 to 15 sprite color selection bit (oc34) 0: color code 0 to 7 1: color code 8 to 15 0 w 5 r osd mode window control bit (oc35) 0: window off 1: window on 0 w 6 r cc mode window control bit (oc36) 0: window off 1: window on 0 w 7 r cdosd mode window control bit (oc37) 0: window off 1: window on after reset rev.1.01 2003.07.16 page 161 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp address 021c 16 address 021d 16 b7 b6 b5 b4 b3 b2 b1 b0 top border control register 1 (tb1) [address 021c 16 ] b name functions after reset rw top border control register 1 0 to 7 control bits of top border (tb10 to tb17) top border position (low-order 8 bits) t h (setting value of low-order 2 bits of tb2 16 2 + setting value of high-order 4 bits of tb1 16 1 + setting value of low-order 4 bits of tb1 16 0 ) indeterminate rw notes 1: do not set 00 16 or 01 16 to the tb1 at tb2 = 00 16 . 2: t h is cycle of h sync . 3: tb2 is top border control register 2. b7 b6 b5 b4 b3 b2 b1 b0 bottom border control register 1 (bb1) [address 021d 16 ] b name functions after reset r w bottom border control register 1 0 to 7 control bits of bottom border (bb10 to bb17) bottom border position (low-order 8 bits) t h (setting value of low-order 2 bits of bb2 16 2 + setting value of high-order 4 bits of bb1 16 1 + setting value of low-order 4 bits of bb1 16 0 ) indeterminate rw notes 1: set values fit for the following condition: (tb1 + tb2 16 2 ) < (bb1 + bb2 16 2 ). 2: t h is cycle of h sync . 3: bb2 is bottom border control reigster 2. m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 162 of 170 address 021e 16 address 021f 16 b7 b6 b5 b4 b3 b2 b1 b0 top border control register 2 (tb2) [address 021e 16 ] b name functions after reset r w top border control register 2 0, 1 control bits of top border (tb20 ,tb21) top border position (high-order 2 bits) t h (setting value of low-order 2 bits of tb2 16 2 + setting value of high-order 4 bits of tb1 16 1 + setting value of low-order 4 bits of tb1 16 0 ) indeterminate rw notes 1: do not set 00 16 or 01 16 to the tb1 at tb2 = 00 16 . 2: t h is cycle of h sync . 3: tb1 is top border control register 1. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are indeterminate. 2 to 7 indetermin ate r b7 b6 b5 b4 b3 b2 b1 b0 bottom border control register 2 (bb2) [address 021f 16 ] b name functions after reset r w bottom border control register 2 0, 1 control bits of bottom border (bb20, bb21) bottom border position (high-order 2 bits) t h (setting value of low-order 2 bits of bb2 16 2 + setting value of high-order 4 bits of bb1 16 1 + setting value of low-order 4 bits of bb1 16 0 ) indeterminate indeterminate rw nothing is assigned. these bits are write disable bits. when these bits are read out, the values are indeterminate. r 2 to 7 notes 1: set values fit for the following condition: (tb1 + tb2 16 2 ) < (bb1 + bb2 16 2 ). 2: t h is cycle of h sync . 3: bb1 is bottom border control reigster 1. rev.1.01 2003.07.16 page 163 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp addresses 0220 16 to 022f 16 addresses 0230 16 to 023f 16 b7 b6 b5 b4 b3 b2 b1 b0 vertical position register 1i (vp1i) (i = 1 to 16) [addresses 0220 16 to 022f 16 ] b name functions after reset rw vertical position register 1i 0 to 7 control bits of vertical display start positions (vp1i0 to vp1i7) (see note 1) vertical display start positions (low-order 8 bits) th (setting value of low-order 2 bits of vp2i 16 2 + setting value of low-order 4 bits of vp1i 16 1 + setting value of low-order 4 bits of vp1i 16 0 ) rw notes 1: do not 00 16 and 01 16 to vp1i at vp2i = 00 16 . 2: t h is cycle of h sync . 3: vp2i is vertical position register 2i. indeterminate b7 b6 b5 b4 b3 b2 b1 b0 vertical position register 2i (vp2i) (i = 1 to 16) [addresses 0230 16 to 023f 16 ] b name functions after reset r w vertical position register 2i 0, 1 control bits of vertical display start positions (vp2i0, vp2i1) (see note 1) vertical display start positions (high-order 2 bits) th (setting value of low-order 2 bits of vp2i 16 2 + setting value of low-order 4 bits of vp1i 16 1 + setting value of low-order 4 bits of vp1i 16 0 ) rw nothing ic assigned. these bits are write disable bits. when these bits are read out, the values are indeterminate. 2 to 7 r notes 1: do not set 00 16 and 01 16 to vp1i at vp2i = 00 16 . 2: t h is cycle of h sync . 3: vp1i is vertical position register 1i. indeterminate indeterminate m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 164 of 170 addresses 0241 16 to 0247 16 , 0249 16 to 024f 16 b7 b6 b5 b4 b3 b2 b1 b0 color pallet register i (cri) (i = 1 to 7, 9to15) [addresses 0241 16 to 0247 16, 0249 16 to 024f 16 ] color pallet register i 0, 1 r signal output control bits (cri0, cri1) indeterminate r w 2, 3 indeterminate r w 4, 5 indeterminate r w indeterminate w 6 7 indeterminate r r g signal output control bits (cri2, cri3) 0 0: no output (see note) 0 1: 1/3 v cc 1 0: 2/3 v cc 11: v cc b0 b1 note: when selecting digital output, the output is v cc at all values other than 00. b signal output control bits (cri4, cri5) out1 signal output control bit (cri6) 0: no output 1: output 0 0: no output (see note) 0 1: 1/3 v cc 1 0: 2/3 v cc 11: v cc b3 b2 0 0: no output (see note) 0 1: 1/3 v cc 1 0: 2/3 v cc 11: v cc b5 b4 b name functions after reset r w nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is indeterminate. rev.1.01 2003.07.16 page 165 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp address 0250 16 address 0251 16 b7 b6 b5 b4 b3 b2 b1 b0 left border control register 1 (lb1) [address 0250 16 ] b name functions after reset rw left border control register 1 0 control bits of left border (lb10 to lb17) 1 r w 1 to 7 0 left border position (low-order 8 bits) t osc (setting value of low-order 3 bits of lb2 16 2 + setting value of high-order 4 bits of lb1 16 1 + setting value of low-order 4 bits of lb1 16 0 ) notes 1: do not set lb1 = lb2 = 00 16 . 2: set values fit for the following condition: (lb1 + lb2 16 2 ) < (rb1 + rb2 16 2 ). 3: t osc is osd oscillation period. 4: lb2 is left border control register 2. b7 b6 b5 b4 b3 b2 b1 b0 left border controlregister 2 (lb2) [address 0251 16 ] b name functions after reset rw left border control register 2 control bits of left border (lb20 to lb22) 0 r w 0 to 2 0 left borderposition (high-order 3 bits) t osc (setting value of low-order 3 bits of lb2 16 2 + setting value of high-order 4 bits of lb1 16 1 + setting value of low-order 4 bits of lb1 16 0 ) nothing is assigned. these bits are write disable bits. when these bits are read out, the values are indeterminate. 3 to 7 r w notes 1: do not set lb1 = lb2 = 00 16 . 2: set values fit for the following condition: (lb1 + lb2 16 2 ) < (rb1 + rb2 16 2 ). 3: t osc is osd oscillation period. 4: lb1 is left border control register 1. m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 166 of 170 address 0252 16 address 0253 16 b7 b6 b5 b4 b3 b2 b1 b0 right border control register 1 (rb1) [address 0252 16 ] b name functions after reset rw right border control register 1 control bits of right border (rb10 to rb17) 1 rw 0 to 7 right border position (low-order 8 bits) t osc (setting value of low-order 3 bits of rb2 16 2 + setting value of high-order 4 bits of rb1 16 1 + setting value of low-order 4 bits of rb1 16 0 ) notes 1: set values fit for the following condition: (lb1 + lb2 16 2 ) < (rb1 + rb2 16 2 ). 2: t osc is osd oscillation period. 3: rb2 is right border control register 2. b7 b6 b5 b4 b3 b2 b1 b0 right border control register 2 (rb2) [address 0253 16 ] b name functions after reset rw right border control register 2 control bits of right border (rb20 to rb22) 1 r w 0 to 2 0 right border position (high-order 3 bits) t osc (setting value of low-order 3 bits of rb2 16 2 + setting value of high-order 4 bits of rb1 16 1 + setting value of low-order 4 bits of rb1 16 0 ) nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0 . 3 to 7 r w notes 1: set values fit for the following condition: (lb1 + lb2 16 2 ) < (rb1 + rb2 16 2 ). 2: t osc is osd oscillation period. 3: rb1 is right border control register 1. rev.1.01 2003.07.16 page 167 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp address 0254 16 address 0255 16 b7 b6 b5 b4 b3 b2 b1 b0 sprite vertical position register 1 (vs1) [address 0254 16 ] b name functions afte reset w sprite vertical position register 1 0 vertical display start position control bits of sprite osd (vs10 to vs17) 1r w 1 to 7 0 vertical display start position (low-order 8 bits) th (setting value of low-order 2 bits of vs2 16 2 + setting value of high-order 4 bits of vs1 16 1 + setting value of low-order 4 bits of vs1 16 0 ) notes 1: do not set 00 16 to the vs1 at vs2 = 00 16 . 2: t h is cycle of h sync . 3: vs2 is sprite vertical position register 2. r b7 b6 b5 b4 b3 b2 b1 b0 sprite vertical position register 2 (vs2) [address 0255 16 ] b name functions after reset w sprite vertical position register 2 vertical start position control bits of sprite osd (vs20, vs21) 0r w 0, 1 0 vertical display start position (high-order 2 bits) t h (setting value of low-order 2 bits of vs2 16 2 + setting value of high-order 4 bits of vs1 16 1 + setting value of low-order 4 bits of vs1 16 0 ) nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0 . 2 to 7 r notes 1: do not set 00 16 to the vs1 at vs2 = 00 16 . 2: t h is cycle of h sync . 3: vs1 is sprite vertical position register 1. r m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 168 of 170 address 0256 16 address 0257 16 b7 b6 b5 b4 b3 b2 b1 b0 sprite horizontal position register 1 (hs1) [address 0256 16 ] b name functions after reset r w sprite horizontal position register 1 0 to 7 horizontal display start position control bits of sprite osd (hs10 tohs17) horizontal display start position (low-order 8 bits) tosc (setting value of low-order 3 bits of hs2 16 2 + setting value of high-order 4 bits of hs1 16 1 + setting value of low-order 4 bits of hs1 16 0 ) indeterminate r w notes 1: do not set hs1 < 30 16 at hs2 = 00 16 . 2: t osc is osd oscillation period. 3: hs2 is sprite horizontal position register 2. b7 b6 b5 b4 b3 b2 b1 b0 sprite horizontal position register 2 (hs2) [address 0257 16 ] b name functions after reset rw sprite horizontal position register 2 0 to 2 horizontal display start position control bits of sprite osd (hs20 to hs22) horizontal display start position (high-order 3 bits) t osc (setting value of low-order 3 bits of hs2 16 2 + setting value of high-order 4 bits of hs1 16 1 + setting value of low-order 4 bits of hs1 16 0 ) indeterminate rw notes 1: do not set hs1< 30 16 at hs2 = 00 16 . 2: t osc is oscillation period. 3: hs1 is sprite horizontal position register 1. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0r 3 to 7 rev.1.01 2003.07.16 page 169 of 170 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp address 0258 16 b7 b6 b5 b4 b3 b2 b1 b0 sprite osd control register (sc) [address 0258 16 ] b name functions after reset rw sprite osd control register 0 sprite osd control bit (sc0) 0rw b3 b2 0 0: 1tc 1/2h 0 1: 1tc 1h 1 0: 2tc 1h 1 1: 2tc 2h 2, 3 dot size selection bits (sc2, sc3) 0rw 4 interrupt occurrence position selection bit (sc4) 0rw 5 0r 1 pre-divide ratio selection bit (sc1) 0: pre-divide ratio 1 1: pre-divide ratio 2 0rw 0: stopped 1: operating 0: after display of horizontal 20 dots 1: after display of horizontal 10 dots or 20 dots notes 1: tc : pre-devided clock period for osd 2: h : h sync x in /4096 sprite interrupt source switch bit (sc5) w 6, 7 0r nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0 . 0: x in /4096 interrupt 1: sprite osd interrupt 19. package outline sdip52-p-600-1.78 weight(g) e jedec code 5.1 eiaj package code lead material alloy 42/cu alloy 52p4b plastic 52pin 600mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 e e e3.8e 0.4 0.5 0.59 0.9 1.0 1.3 0.65 0.75 1.05 0.22 0.27 0.34 45.65 45.85 46.05 12.85 13.0 13.15 e 1.778 e e 15.24 e 3.0 e e 0 m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev.1.01 2003.07.16 page 170 of 170 keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but ther e is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation p roduct best suited to the customer s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporat ion or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reas ons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest produ ct information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracie s or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas te chnology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp oration assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used un der circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor wh en considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or u ndersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com copyright ? 2003. renesas technology corporation, all rights reserved. printed in japan. m37281mah xxxsp,m37281mfh xxxsp,m37281mkh xxxsp, m37281eksp rev. rev. no. date 1.00 first edition 0111 1.01 p128 16. prom programming method name of programming adapter pca7401 is 0307 changed to pca7400. m37281mah xxxsp,m37281mfh xxxsp m37281mkh xxxsp,m37281eksp(rev.1.0) data sheet (1/1) revision description revision description list |
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